JP6378117B2 - アライメントマークの形成方法および半導体装置 - Google Patents
アライメントマークの形成方法および半導体装置 Download PDFInfo
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- JP6378117B2 JP6378117B2 JP2015051208A JP2015051208A JP6378117B2 JP 6378117 B2 JP6378117 B2 JP 6378117B2 JP 2015051208 A JP2015051208 A JP 2015051208A JP 2015051208 A JP2015051208 A JP 2015051208A JP 6378117 B2 JP6378117 B2 JP 6378117B2
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- film
- alignment mark
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
- H01L21/02354—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light using a coherent radiation, e.g. a laser
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
- H01L2223/5446—Located in scribe lines
Description
図1は、第1の実施形態が適用される半導体装置の製造方法の手順の一例を模式的に示す断面図である。なお、ここでは、後述する半導体チップ領域2での半導体装置の製造方法の手順を示している。
第1の実施形態では、アライメントマークの上面は、層間絶縁膜の上面と一致する場合を示した。第2の実施形態では、アライメントマークの上面が、層間絶縁膜の上面よりも突出する場合の半導体装置とアライメントマークの形成方法について説明する。
Claims (5)
- 絶縁膜に第1パターンを形成し、
前記絶縁膜の前記第1パターンの形成位置を含む領域上に第1透明膜を形成し、
前記第1透明膜の上に可視光領域の光に対して不透明な不透明膜を形成し、
前記第1透明膜と接する前記不透明膜を選択的に酸化させて第2透明膜を生成するアライメントマークの形成方法。 - 前記第1透明膜は、酸素を含む材料によって構成される請求項1に記載のアライメントマークの形成方法。
- 前記不透明膜は、酸化によって透過率が上昇する材料である請求項1に記載のアライメントマークの形成方法。
- 前記第2透明膜の生成では、少なくとも前記第1透明膜と接する前記不透明膜を400度以上の温度でアニールする請求項1に記載のアライメントマークの形成方法。
- 基板上に、素子が配置される第1領域と、素子が配置されない第2領域と、が設けられ、前記第2領域にアライメントマークを備える半導体装置であって、
前記第1領域の絶縁膜上に配置される配線層を備え、
前記アライメントマークは、
前記第2領域の前記絶縁膜中に埋め込まれる所定形状の金属パターンと、
前記金属パターンを含む領域の前記絶縁膜上に配置される第1透明膜と、
前記第1透明膜を覆う第2透明膜と、
を備え、
前記第2透明膜は、前記配線層を構成する材料の酸化物であり、
前記金属パターンの上面は、前記絶縁膜の上面よりも下方に位置する半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015051208A JP6378117B2 (ja) | 2015-03-13 | 2015-03-13 | アライメントマークの形成方法および半導体装置 |
US14/799,787 US9502357B2 (en) | 2015-03-13 | 2015-07-15 | Alignment mark formation method and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015051208A JP6378117B2 (ja) | 2015-03-13 | 2015-03-13 | アライメントマークの形成方法および半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2016170350A JP2016170350A (ja) | 2016-09-23 |
JP6378117B2 true JP6378117B2 (ja) | 2018-08-22 |
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JP2015051208A Expired - Fee Related JP6378117B2 (ja) | 2015-03-13 | 2015-03-13 | アライメントマークの形成方法および半導体装置 |
Country Status (2)
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US (1) | US9502357B2 (ja) |
JP (1) | JP6378117B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200015775A (ko) * | 2017-07-17 | 2020-02-12 | 에이에스엠엘 네델란즈 비.브이. | 정보 결정 장치 및 방법 |
US11244907B2 (en) * | 2020-01-02 | 2022-02-08 | International Business Machines Corporation | Metal surface preparation for increased alignment contrast |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2754609B2 (ja) * | 1988-06-08 | 1998-05-20 | 日本電気株式会社 | 半導体装置の製造方法 |
EP0570740B1 (en) * | 1992-04-30 | 1999-07-21 | Canon Kabushiki Kaisha | Image forming method, image forming apparatus and transparent film |
JPH0846043A (ja) * | 1994-08-04 | 1996-02-16 | Toshiba Corp | 半導体装置の多層配線構造及びその形成方法 |
AU1174599A (en) * | 1997-11-20 | 1999-06-15 | Nikon Corporation | Mark detection method and mark position sensor |
JP4864776B2 (ja) * | 2007-03-14 | 2012-02-01 | 株式会社東芝 | フォトマスク |
JP4967904B2 (ja) * | 2007-07-31 | 2012-07-04 | 富士電機株式会社 | 半導体装置 |
JP2009088140A (ja) | 2007-09-28 | 2009-04-23 | Fujifilm Corp | アライメントマーク構造、半導体素子製造方法、半導体素子、電荷結合素子、及び固体撮像装置 |
US8324742B2 (en) * | 2008-04-01 | 2012-12-04 | Texas Instruments Incorporated | Alignment mark for opaque layer |
JP5337234B2 (ja) * | 2009-03-09 | 2013-11-06 | 株式会社東芝 | 情報記録再生装置及びその製造方法 |
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2015
- 2015-03-13 JP JP2015051208A patent/JP6378117B2/ja not_active Expired - Fee Related
- 2015-07-15 US US14/799,787 patent/US9502357B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US9502357B2 (en) | 2016-11-22 |
JP2016170350A (ja) | 2016-09-23 |
US20160268211A1 (en) | 2016-09-15 |
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