JP6333894B2 - 配線基板、配線基板の製造方法、電子部品、および電子部品の製造方法 - Google Patents

配線基板、配線基板の製造方法、電子部品、および電子部品の製造方法 Download PDF

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Publication number
JP6333894B2
JP6333894B2 JP2016136037A JP2016136037A JP6333894B2 JP 6333894 B2 JP6333894 B2 JP 6333894B2 JP 2016136037 A JP2016136037 A JP 2016136037A JP 2016136037 A JP2016136037 A JP 2016136037A JP 6333894 B2 JP6333894 B2 JP 6333894B2
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JP
Japan
Prior art keywords
conductor
chip
wiring board
bonding
layer
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Active
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JP2016136037A
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English (en)
Japanese (ja)
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JP2018006702A (ja
Inventor
善夏 黄
善夏 黄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Towa Corp
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Towa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Towa Corp filed Critical Towa Corp
Priority to JP2016136037A priority Critical patent/JP6333894B2/ja
Priority to CN201780042267.9A priority patent/CN109478536A/zh
Priority to KR1020187036756A priority patent/KR102254999B1/ko
Priority to PCT/JP2017/014101 priority patent/WO2018008214A1/ja
Priority to MYPI2019000001A priority patent/MY192589A/en
Priority to TW106111861A priority patent/TWI650051B/zh
Publication of JP2018006702A publication Critical patent/JP2018006702A/ja
Application granted granted Critical
Publication of JP6333894B2 publication Critical patent/JP6333894B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2016136037A 2016-07-08 2016-07-08 配線基板、配線基板の製造方法、電子部品、および電子部品の製造方法 Active JP6333894B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2016136037A JP6333894B2 (ja) 2016-07-08 2016-07-08 配線基板、配線基板の製造方法、電子部品、および電子部品の製造方法
CN201780042267.9A CN109478536A (zh) 2016-07-08 2017-04-04 布线基板、布线基板的制造方法、电子零件以及电子零件的制造方法
KR1020187036756A KR102254999B1 (ko) 2016-07-08 2017-04-04 배선 기판, 배선 기판의 제조 방법, 전자 부품, 및 전자 부품의 제조 방법
PCT/JP2017/014101 WO2018008214A1 (ja) 2016-07-08 2017-04-04 配線基板、配線基板の製造方法、電子部品、および電子部品の製造方法
MYPI2019000001A MY192589A (en) 2016-07-08 2017-04-04 Wiring substrate, method for manufacturing wiring substrate, electronic component, and method for manufacturing electronic component
TW106111861A TWI650051B (zh) 2016-07-08 2017-04-10 配線基板、配線基板之製造方法、電子元件以及電子元件之製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016136037A JP6333894B2 (ja) 2016-07-08 2016-07-08 配線基板、配線基板の製造方法、電子部品、および電子部品の製造方法

Publications (2)

Publication Number Publication Date
JP2018006702A JP2018006702A (ja) 2018-01-11
JP6333894B2 true JP6333894B2 (ja) 2018-05-30

Family

ID=60912065

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016136037A Active JP6333894B2 (ja) 2016-07-08 2016-07-08 配線基板、配線基板の製造方法、電子部品、および電子部品の製造方法

Country Status (6)

Country Link
JP (1) JP6333894B2 (zh)
KR (1) KR102254999B1 (zh)
CN (1) CN109478536A (zh)
MY (1) MY192589A (zh)
TW (1) TWI650051B (zh)
WO (1) WO2018008214A1 (zh)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003303859A (ja) * 2002-04-10 2003-10-24 Hitachi Cable Ltd 半導体装置用テープキャリアおよびその製造方法
US7164192B2 (en) * 2003-02-10 2007-01-16 Skyworks Solutions, Inc. Semiconductor die package with reduced inductance and reduced die attach flow out
JP2005116909A (ja) * 2003-10-10 2005-04-28 Hitachi Cable Ltd 電子装置及び電子装置に用いる配線板
JP2011029518A (ja) * 2009-07-28 2011-02-10 Shindo Denshi Kogyo Kk フレキシブルプリント配線板、半導体装置及びその製造方法
JP5848976B2 (ja) * 2012-01-25 2016-01-27 新光電気工業株式会社 配線基板、発光装置及び配線基板の製造方法

Also Published As

Publication number Publication date
WO2018008214A1 (ja) 2018-01-11
KR102254999B1 (ko) 2021-05-24
CN109478536A (zh) 2019-03-15
JP2018006702A (ja) 2018-01-11
MY192589A (en) 2022-08-29
TWI650051B (zh) 2019-02-01
TW201804881A (zh) 2018-02-01
KR20190025835A (ko) 2019-03-12

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