JP6322044B2 - Iii−v族デバイスおよびその製造方法 - Google Patents
Iii−v族デバイスおよびその製造方法 Download PDFInfo
- Publication number
- JP6322044B2 JP6322044B2 JP2014098017A JP2014098017A JP6322044B2 JP 6322044 B2 JP6322044 B2 JP 6322044B2 JP 2014098017 A JP2014098017 A JP 2014098017A JP 2014098017 A JP2014098017 A JP 2014098017A JP 6322044 B2 JP6322044 B2 JP 6322044B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- iii
- group
- compound
- buffer layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
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- H10P14/3414—
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- H10P14/20—
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- H10P14/24—
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- H10P14/27—
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- H10P14/2905—
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- H10P14/3211—
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- H10P14/3218—
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- H10P14/3221—
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- H10P14/3418—
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- H10P14/3421—
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- H10P14/3422—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP20130168201 EP2804203A1 (en) | 2013-05-17 | 2013-05-17 | III-V device and method for manufacturing thereof |
| EP13168201.5 | 2013-05-17 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014229900A JP2014229900A (ja) | 2014-12-08 |
| JP2014229900A5 JP2014229900A5 (enExample) | 2018-03-01 |
| JP6322044B2 true JP6322044B2 (ja) | 2018-05-09 |
Family
ID=48446159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014098017A Active JP6322044B2 (ja) | 2013-05-17 | 2014-05-09 | Iii−v族デバイスおよびその製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9082616B2 (enExample) |
| EP (1) | EP2804203A1 (enExample) |
| JP (1) | JP6322044B2 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9835570B2 (en) * | 2013-09-13 | 2017-12-05 | The United States Of America As Represented By The Administrator Of Nasa | X-ray diffraction (XRD) characterization methods for sigma=3 twin defects in cubic semiconductor (100) wafers |
| JP6153224B2 (ja) * | 2013-09-20 | 2017-06-28 | 国立研究開発法人物質・材料研究機構 | 表面の平坦性および結晶構造の完全性に優れたGaSb/InAs/Si(111)構造とその形成方法、並びにその構造を用いたMOSデバイスおよび赤外線検出デバイス |
| JP6465785B2 (ja) * | 2015-10-14 | 2019-02-06 | クアーズテック株式会社 | 化合物半導体基板 |
| CN105762064B (zh) * | 2016-02-06 | 2020-08-21 | 上海新傲科技股份有限公司 | 用于氮化物生长硅衬底实时图形化的方法 |
| TWI622171B (zh) | 2016-06-24 | 2018-04-21 | 財團法人國家實驗研究院 | 異質整合半導體裝置及其製造方法 |
| WO2023091693A1 (en) * | 2021-11-18 | 2023-05-25 | Meta Platforms Technologies, Llc | Red light-emitting diode with phosphide epitaxial heterostructure grown on silicon |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3855061B2 (ja) | 2003-09-08 | 2006-12-06 | 独立行政法人情報通信研究機構 | Si基板上への化合物半導体薄膜形成方法 |
| JP5063594B2 (ja) * | 2005-05-17 | 2012-10-31 | 台湾積體電路製造股▲ふん▼有限公司 | 転位欠陥密度の低い格子不整合半導体構造およびこれに関連するデバイス製造方法 |
| US7851780B2 (en) | 2006-08-02 | 2010-12-14 | Intel Corporation | Semiconductor buffer architecture for III-V devices on silicon substrates |
| US7573059B2 (en) | 2006-08-02 | 2009-08-11 | Intel Corporation | Dislocation-free InSb quantum well structure on Si using novel buffer architecture |
| US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
| KR20100096084A (ko) * | 2007-12-28 | 2010-09-01 | 스미또모 가가꾸 가부시키가이샤 | 반도체 기판, 반도체 기판의 제조 방법 및 전자 디바이스 |
| JP2010245435A (ja) * | 2009-04-09 | 2010-10-28 | Hitachi Cable Ltd | 発光素子用エピタキシャルウェハおよびその製造方法 |
| KR20120022872A (ko) * | 2009-05-22 | 2012-03-12 | 스미또모 가가꾸 가부시키가이샤 | 반도체 기판, 전자 디바이스, 반도체 기판의 제조 방법 및 전자 디바이스의 제조 방법 |
| CN102449785A (zh) * | 2009-06-05 | 2012-05-09 | 住友化学株式会社 | 光器件、半导体基板、光器件的制造方法、以及半导体基板的制造方法 |
| US9601328B2 (en) | 2009-10-08 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Growing a III-V layer on silicon using aligned nano-scale patterns |
| US8609517B2 (en) * | 2010-06-11 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOCVD for growing III-V compound semiconductors on silicon substrates |
| EP2423951B1 (en) | 2010-08-05 | 2016-07-20 | Imec | Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof |
| US8183134B2 (en) * | 2010-10-19 | 2012-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method with improved epitaxial quality of III-V compound on silicon surfaces |
-
2013
- 2013-05-17 EP EP20130168201 patent/EP2804203A1/en not_active Withdrawn
-
2014
- 2014-05-09 JP JP2014098017A patent/JP6322044B2/ja active Active
- 2014-05-15 US US14/279,033 patent/US9082616B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US9082616B2 (en) | 2015-07-14 |
| EP2804203A1 (en) | 2014-11-19 |
| US20140339680A1 (en) | 2014-11-20 |
| JP2014229900A (ja) | 2014-12-08 |
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