JP6263534B2 - ガラス基板の製造方法、ガラス基板、および、ディスプレイ用パネル - Google Patents
ガラス基板の製造方法、ガラス基板、および、ディスプレイ用パネル Download PDFInfo
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- JP6263534B2 JP6263534B2 JP2015528306A JP2015528306A JP6263534B2 JP 6263534 B2 JP6263534 B2 JP 6263534B2 JP 2015528306 A JP2015528306 A JP 2015528306A JP 2015528306 A JP2015528306 A JP 2015528306A JP 6263534 B2 JP6263534 B2 JP 6263534B2
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Images
Classifications
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
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Description
本発明の実施形態について、図面を参照しながら説明する。本実施形態で用いられるガラス基板の製造方法によって製造されるガラス基板10は、液晶ディスプレイ、プラズマディスプレイおよび有機ELディスプレイ等のフラットパネルディスプレイ(FPD)の製造に用いられる。ガラス基板10は、太陽電池パネルの製造にも用いられる。ガラス基板10は、例えば、0.2mm〜0.8mmの厚みを有し、かつ、縦680mm〜2200mmおよび横880mm〜2500mmのサイズを有する。
(b)Al2O3:10質量%〜25質量%、
(c)B2O3:5質量%〜18質量%、
(d)MgO:0質量%〜10質量%、
(e)CaO:0質量%〜20質量%、
(f)SrO:0質量%〜20質量%、
(g)BaO:0質量%〜10質量%、
(h)RO:5質量%〜20質量%(Rは、Mg、Ca、SrおよびBaから選択される少なくとも1種である。)、
(i)R’2O:0質量%〜2.0質量%(R’は、Li、NaおよびKから選択される少なくとも1種である。)、
(j)SnO2、Fe2O3およびCeO2から選ばれる少なくとも1種の金属酸化物。
粗面化工程S80で行われる、粗面化面14の表面処理について説明する。図3は、ガラス基板10の浸水式エッチング処理を行う浸水式エッチング装置20の概略図である。浸水式エッチング装置20は、複数のガラス基板10を収容可能なカセット22と、カセット22を搬送する搬送機構(図示せず)と、エッチング液槽24とを備えている。エッチング液槽24は、必要に応じて、超音波機構および温度調節機構を備えている。超音波機構は、ガラス基板10がエッチング液26に浸漬された状態で、超音波によりガラス基板10を洗浄し、かつ、ガラス基板10表面のエッチング処理を促進する。温度調節機構は、エッチング液26の温度を調節する。浸水式エッチング装置20は、さらに、エッチング液槽24にエッチング液26を供給するタンク(図示せず)を備えている。
粗面化工程S80において表面処理された粗面化面14について説明する。粗面化面14は、粗面化工程S80のエッチング工程によって、微小な凹凸が形成される面である。
FPDの製造工程において、ガラス基板10の素子形成面12には、TFT等の半導体素子、具体的には、ポリシリコン薄膜およびITO薄膜等からなる複数層の薄膜が形成される。素子形成面12に成膜処理が行われる度に、ガラス基板10は、半導体製造装置の反応容器内のサセプタから取り外される。このとき、ガラス基板10を載置するサセプタの金属表面と、ガラス基板10の粗面化面14との間において、剥離帯電が発生する。剥離帯電によってガラス基板10に静電気が蓄積されると、ガラス基板10の粗面化面14は、サセプタの金属表面に対して、静電気によって貼り付きやすくなる。これにより、ガラス基板10をサセプタから取り外す際に、ガラス基板10に過度な力を与えることでガラス基板10を破損させてしまう場合がある。また、剥離帯電によって蓄積された静電気に起因する電圧は、ガラス基板10の素子形成面12に形成された半導体素子等を破壊してしまう場合がある。また、液晶パネル製造工程において、TFTパネルまたはCFパネルに静電気が帯電した状態で、TFTパネルとCFパネルとが貼り合わせられて液晶が注入されると、製造された液晶パネルの表示にムラが生じる場合がある。そのため、FPDの製造工程では、ガラス基板10の帯電を抑制することが重要である。
以上、本発明に係るガラス基板の製造方法について説明したが、本発明は上記の実施形態に限定されず、本発明の主旨を逸脱しない範囲において、種々の改良および変更が施されてもよい。なお、本発明は、半導体素子が表面に形成されるガラス基板だけでなく、カラーフィルタが表面に形成されるガラス基板にも効果を奏する。
本実施形態では、浸水式エッチング処理により、ガラス基板10の粗面化面14が粗面化されるが、浸水式エッチング処理の前に、粗面化面14の洗浄処理が行われてもよい。洗浄処理は、例えば、大気圧プラズマ洗浄処理である。大気圧プラズマ洗浄処理では、例えば、窒素および酸素の混合ガスである空気、および、アルゴンから生成される、プラズマ状態で活性化されたガスが用いられる。
本実施形態では、ウエットエッチング処理は、浸水式エッチング処理であるが、ロールエッチング処置およびシャワーエッチング処置等でもよい。ロールエッチング処理およびシャワーエッチング処理では、浸水式エッチング処理と比べて、粗面化面14がエッチャントと接する時間である接液時間が短く、かつ、接液時間を制御しにくい。そのため、ロールエッチング処理およびシャワーエッチング処理では、浸水式エッチング処理の場合よりもエッチャントに含まれるフッ化水素の濃度を高くすることが好ましく、かつ、フッ化水素の濃度を調節することにより粗面化面14に形成される凸部の分散を制御することが好ましい。ロールエッチング処理およびシャワーエッチング処理の場合、エッチャントに含まれるフッ化水素の濃度は、2000ppm〜8000ppmであることが好ましい。
本実施形態では、ガラス基板10全体をエッチング液に浸漬する浸水式エッチング処理により、ガラス基板10の素子形成面12および粗面化面14の両方が粗面化されるが、粗面化面14のみが粗面化されてもよい。粗面化面14のみを粗面化するエッチング処理としては、ドライエッチング処理およびウエットエッチング処理等のケミカルエッチング処理がある。ケミカルエッチング処理では、フッ素系のエッチャントが用いられ、特に、フッ化水素を含むエッチャントが用いられることが好ましい。
図8では、ガラス基板10の粗面化面14のウエットエッチング処理の例として、粗面化ローラ44を用いて粗面化面14にエッチング液を塗布するローラエッチング処理について説明した。しかし、粗面化面14のウエットエッチング処理は、例えば、シャワーエッチング処理であってもよい。
12 素子形成面(第2主表面)
14 粗面化面(第1主表面)
Claims (10)
- ディスプレイ用のガラス基板の製造方法であって、
ガラス基板を製造する製造工程と、
前記ガラス基板の一方の主表面であるガラス表面に凹凸を形成する表面処理を行う表面処理工程と、
を有し、
前記表面処理工程では、
前記ガラス表面に、その粗さ曲線の平均線からの高さが1nm以上である凸部が分散して形成され、
一辺の長さが1μmの正方形の形状を有し前記ガラス表面の一部を占める矩形領域に関して、任意の前記矩形領域の面積に占める前記凸部の面積の比率である凸部面積比率が0.5%〜10%となるように、前記表面処理が行われ、
正方形の形状を有する少なくとも100個の分割領域に前記矩形領域が均等に分割される場合において、前記矩形領域に含まれる前記分割領域の数に占める、前記凸部を有する前記分割領域の数の比率である凸部含有比率が80%以上となるように、前記表面処理が行われ、
前記ガラス基板は、アルカリ成分として、R’ 2 O(R’は、Li、NaおよびKから選択される少なくとも1種である。)を0質量%〜2.0質量%含み、
前記ガラス表面と反対側の前記主表面は、半導体素子が形成されるデバイス面であり、
前記半導体素子は、配線の最小線幅が4μm未満であり、ゲート絶縁膜の膜厚が100nm未満であるTFTである、
ガラス基板の製造方法。 - 前記凸部面積比率は、0.75%〜7.0%である、
請求項1に記載のガラス基板の製造方法。 - 前記凸部含有比率は、90%以上である、
請求項1または2に記載のガラス基板の製造方法。 - 前記表面処理は、ケミカルエッチング処理である、
請求項1〜3のいずれか1項に記載のガラス基板の製造方法。 - 前記デバイス面は、低温ポリシリコン半導体または酸化物半導体が形成される面である、
請求項1〜4のいずれか1項に記載のガラス基板の製造方法。 - 前記ガラス基板は、Si、AlおよびBを組成として含むボロアルミノシリケートガラスからなる、
請求項1〜5のいずれか1項に記載のガラス基板の製造方法。 - ディスプレイ用のガラス基板であって、
前記ガラス基板の一方の主表面であるガラス表面に、その粗さ曲線の平均線からの高さが1nm以上である凸部が分散して形成され、
一辺の長さが1μmの正方形の形状を有し前記ガラス表面の一部を占める矩形領域に関して、任意の前記矩形領域の面積に占める前記凸部の面積の比率である凸部面積比率が0.5%〜10%であり、
正方形の形状を有する少なくとも100個の分割領域に前記矩形領域が均等に分割される場合において、前記矩形領域に含まれる前記分割領域の数に占める、前記凸部を有する前記分割領域の数の比率である凸部含有比率が80%以上であり、
アルカリ成分として、R’ 2 O(R’は、Li、NaおよびKから選択される少なくとも1種である。)を0質量%〜2.0質量%含み、
前記ガラス表面と反対側の前記主表面は、半導体素子が形成されるデバイス面であり、
前記半導体素子は、配線の最小線幅が4μm未満であり、ゲート絶縁膜の膜厚が100nm未満であるTFTである、
ガラス基板。 - 前記デバイス面は、低温ポリシリコン半導体または酸化物半導体が形成される面である、
請求項7に記載のガラス基板。 - Si、AlおよびBを組成として含むボロアルミノシリケートガラスからなる、
請求項7または8に記載のガラス基板。 - 半導体素子が形成されたガラス基板であるディスプレイ用パネルであって、
前記ガラス基板の一方の主表面であって、その粗さ曲線の平均線からの高さが1nm以上である凸部が分散して形成される第1主表面と、
前記第1主表面と反対側の前記主表面であって、半導体素子が形成される第2主表面と、
を備え、
一辺の長さが1μmの正方形の形状を有し前記第1主表面の一部を占める矩形領域に関して、任意の前記矩形領域の面積に占める前記凸部の面積の比率である凸部面積比率が0.5%〜10%であり、
正方形の形状を有する少なくとも100個の分割領域に前記矩形領域が均等に分割される場合において、前記矩形領域に含まれる前記分割領域の数に占める、前記凸部を有する前記分割領域の数の比率である凸部含有比率が80%以上であり、
前記ガラス基板は、アルカリ成分として、R’ 2 O(R’は、Li、NaおよびKから選択される少なくとも1種である。)を0質量%〜2.0質量%含み、
配線の最小線幅が4μm未満であり、ゲート絶縁膜の膜厚が100nm未満である回路を有するTFTパネルである、
ディスプレイ用パネル。
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TWI599547B (zh) | 2017-09-21 |
TW201504176A (zh) | 2015-02-01 |
JPWO2015012307A1 (ja) | 2017-03-02 |
KR101932329B1 (ko) | 2018-12-24 |
KR20160060033A (ko) | 2016-05-27 |
CN105492404B (zh) | 2018-09-11 |
WO2015012307A1 (ja) | 2015-01-29 |
CN105492404A (zh) | 2016-04-13 |
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