JP6199322B2 - 制御されたキャビティｍｅｍｓパッケージを集積化ボードに埋め込むための方法 - Google Patents

制御されたキャビティｍｅｍｓパッケージを集積化ボードに埋め込むための方法 Download PDF

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JP6199322B2
JP6199322B2 JP2014559988A JP2014559988A JP6199322B2 JP 6199322 B2 JP6199322 B2 JP 6199322B2 JP 2014559988 A JP2014559988 A JP 2014559988A JP 2014559988 A JP2014559988 A JP 2014559988A JP 6199322 B2 JP6199322 B2 JP 6199322B2
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mems
plate
cavity
chip
radiation
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JP2015517919A (ja
JP2015517919A5 (enExample
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ディー マナック クリストファー
ディー マナック クリストファー
ステップニアク フランク
ステップニアク フランク
ケイ コドゥリ スリーニーバサン
ケイ コドゥリ スリーニーバサン
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日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0067—Packages or encapsulation for controlling the passage of optical signals through the package
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/02—Constructional details
    • G01J5/04—Casings
    • G01J5/041—Mountings in enclosures or in a particular environment
    • G01J5/045—Sealings; Vacuum enclosures; Encapsulated packages; Wafer bonding structures; Getter arrangements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
    • G01J5/12—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using thermoelectric elements, e.g. thermocouples
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0207—Bolometers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
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    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/1026—Compound semiconductors
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    • H01L2924/14—Integrated circuits
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    • H01L2924/146—Mixed devices
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)
  • Radiation Pyrometers (AREA)
JP2014559988A 2012-02-27 2013-02-27 制御されたキャビティｍｅｍｓパッケージを集積化ボードに埋め込むための方法 Active JP6199322B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/405,513 US8866237B2 (en) 2012-02-27 2012-02-27 Methods for embedding controlled-cavity MEMS package in integration board
US13/405,513 2012-02-27
PCT/US2013/027989 WO2013130582A1 (en) 2012-02-27 2013-02-27 Method for embedding controlled-cavity mems package in integration board

Publications (3)

Publication Number Publication Date
JP2015517919A JP2015517919A (ja) 2015-06-25
JP2015517919A5 JP2015517919A5 (enExample) 2016-03-24
JP6199322B2 true JP6199322B2 (ja) 2017-09-20

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US (2) US8866237B2 (enExample)
JP (1) JP6199322B2 (enExample)
CN (1) CN104136365B (enExample)
WO (1) WO2013130582A1 (enExample)

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CN111901731B (zh) * 2019-05-06 2022-01-07 奥音科技（北京）有限公司 电动声学换能器及其制造方法
US11289396B2 (en) * 2019-09-29 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Sensing component encapsulated by an encapsulation layer with a roughness surface having a hollow region
CN112073850B (zh) * 2020-08-27 2021-12-24 瑞声新能源发展(常州)有限公司科教城分公司 扬声器箱
US20220270960A1 (en) * 2021-02-23 2022-08-25 Texas Instruments Incorporated Open-Cavity Package for Chip Sensor
US20220415762A1 (en) * 2021-06-27 2022-12-29 Texas Instruments Incorporated Semiconductor package with drilled mold cavity
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US20150004739A1 (en) 2015-01-01
US20130221455A1 (en) 2013-08-29
WO2013130582A1 (en) 2013-09-06
US8866237B2 (en) 2014-10-21
JP2015517919A (ja) 2015-06-25
US9321631B2 (en) 2016-04-26
CN104136365A (zh) 2014-11-05

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