JP6182548B2 - 圧縮可能な構造を用いたマルチチップモジュールにおけるアライメントの維持 - Google Patents

圧縮可能な構造を用いたマルチチップモジュールにおけるアライメントの維持 Download PDF

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JP6182548B2
JP6182548B2 JP2014557785A JP2014557785A JP6182548B2 JP 6182548 B2 JP6182548 B2 JP 6182548B2 JP 2014557785 A JP2014557785 A JP 2014557785A JP 2014557785 A JP2014557785 A JP 2014557785A JP 6182548 B2 JP6182548 B2 JP 6182548B2
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mcm
bridge
tip
compressible structure
island
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JP2015524155A (ja
JP2015524155A5 (enExample
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タッカー，ヒレン・ディ
ヤン，ヒュン・スク
シュビン，アイバン
カニンガム，ジョン・イー
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オラクル・インターナショナル・コーポレイション
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L2924/351—Thermal stress
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    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Connector Housings Or Holding Contact Members (AREA)
JP2014557785A 2012-02-15 2013-02-14 圧縮可能な構造を用いたマルチチップモジュールにおけるアライメントの維持 Active JP6182548B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/397,593 2012-02-15
US13/397,593 US8742576B2 (en) 2012-02-15 2012-02-15 Maintaining alignment in a multi-chip module using a compressible structure
PCT/US2013/026223 WO2013123259A2 (en) 2012-02-15 2013-02-14 Maintaining alignment in a multi-chip module using a compressible structure

Publications (3)

Publication Number Publication Date
JP2015524155A JP2015524155A (ja) 2015-08-20
JP2015524155A5 JP2015524155A5 (enExample) 2016-02-12
JP6182548B2 true JP6182548B2 (ja) 2017-08-16

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US (1) US8742576B2 (enExample)
EP (1) EP2815429B1 (enExample)
JP (1) JP6182548B2 (enExample)
CN (1) CN104471709B (enExample)
TW (1) TWI550821B (enExample)
WO (1) WO2013123259A2 (enExample)

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US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) * 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
KR101815489B1 (ko) * 2014-02-26 2018-01-05 인텔 코포레이션 스루 브리지 도전성 비아 신호 접속에 의한 임베딩된 멀티디바이스 브리지
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
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