JP6173505B2 - 主結晶方向に対し傾斜した長手方向軸を有するトレンチゲート構造を含む電力半導体デバイス - Google Patents
主結晶方向に対し傾斜した長手方向軸を有するトレンチゲート構造を含む電力半導体デバイス Download PDFInfo
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- JP6173505B2 JP6173505B2 JP2016041251A JP2016041251A JP6173505B2 JP 6173505 B2 JP6173505 B2 JP 6173505B2 JP 2016041251 A JP2016041251 A JP 2016041251A JP 2016041251 A JP2016041251 A JP 2016041251A JP 6173505 B2 JP6173505 B2 JP 6173505B2
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Description
Claims (20)
- 半導体デバイスにおいて、
水平面に平行な第1主結晶方向(401)を有する半導体ボディ(100)と、
長手方向に延在する長さが前記水平面における幅よりも長いトレンチゲート構造(150)と、
隣り合う複数のトレンチゲート構造(150)間に位置するメサ部(170)と、
を含み、
前記トレンチゲート構造の長手方向軸(159)は、前記水平面において最小で2°、最大で30°の傾斜角(φ)だけ、前記第1主結晶方向(401)に対し傾斜しており、
前記メサ部(170)において、第1メサ側壁(104)の第1側壁セクション(104a)は、前記第1主結晶方向(401)に平行な主結晶面であり、前記第1側壁セクション(104a)に対し傾斜した第2側壁セクション(104b)によって、複数の前記第1側壁セクション(104a)が連結されている、
半導体デバイス。 - 前記水平面は、前記半導体ボディ(100)の平均表面(101x)に平行である、
請求項1記載の半導体デバイス。 - 前記第1主結晶方向(401)と直交する第2主結晶方向(402)が、前記水平面に対し最小で2°のオフ角(α)で傾斜している、
請求項1または2記載の半導体デバイス。 - 前記半導体ボディ(100)の第1表面(101)は、第1表面セクション(101a)と、前記第1表面セクション(101a)に対し傾斜した第2表面セクション(101b)と、を含み、前記第2表面セクション(101b)によって、複数の前記第1表面セクション(101a)が連結されている、
請求項1から3のいずれか1項記載の半導体デバイス。 - 前記第1表面セクション(101a)は、前記第1主結晶方向(401)と直交する第2主結晶方向(402)に平行な主結晶面である、
請求項4記載の半導体デバイス。 - 前記第1主結晶方向(401)と直交する第2主結晶方向(402)が、前記水平面に対し3°〜12°の範囲のオフ角(α)で傾斜している、
請求項1から5のいずれか1項記載の半導体デバイス。 - 前記傾斜角(φ)は3°〜12°の範囲にある、
請求項1から6のいずれか1項記載の半導体デバイス。 - 前記半導体ボディ(100)は六方晶格子を有しており、前記第1主結晶方向(401)は、<11−20>結晶方向と<1−100>結晶方向とのうちの一方である、
請求項1から7のいずれか1項記載の半導体デバイス。 - 前記半導体ボディ(100)の第1表面(101)は、(1−100)結晶面により形成された第1表面セクション(101a)と、前記第1表面セクション(101a)に対し0°よりも大きい角度で傾斜した第2表面セクション(101b)と、を含み、前記第2表面セクション(101b)によって、複数の前記第1表面セクション(101a)が連結されている、
請求項1から8のいずれか1項記載の半導体デバイス。 - 前記半導体ボディ(100)の第1表面(101)は、(11−20)結晶面により形成された第1表面セクション(101a)と、前記第1表面セクション(101a)に対し0°よりも大きい角度で傾斜した第2表面セクション(101b)と、を含み、前記第2表面セクション(101b)によって、複数の前記第1表面セクション(101a)が連結されている、
請求項1から8のいずれか1項記載の半導体デバイス。 - 前記半導体ボディ(100)は、4Hポリタイプの炭化ケイ素をベースとしている、
請求項1から10のいずれか1項記載の半導体デバイス。 - 前記メサ部(170)は、ボディゾーン(115)を有しており、
前記ボディゾーン(115)は、ドリフト構造(120)とともに第1pn接合部(pn1)を形成し、ソースゾーン(110)とともに第2pn接合部(pn2)を形成し
前記ソースゾーン(110)は、前記ボディゾーン(115)と前記半導体ボディ(100)の平均表面(101x)との間に形成されている、
請求項1から11のいずれか1項記載の半導体デバイス。 - ダイオード領域(116)が設けられており、前記ダイオード領域(116)は、前記ドリフト構造(120)とともに第3pn接合部を形成しており、前記トレンチゲート構造(150)の下に部分的に延在している、
請求項12記載の半導体デバイス。 - 前記トレンチゲート構造(150)は、±1°を超えない大きさでオフ角度(α)から偏位したテーパ角(β)で先細りしている、
請求項1から13のいずれか1項記載の半導体デバイス。 - 前記トレンチゲート構造(150)の深さは、0.5μm〜2.0μmの範囲にある、
請求項1から13のいずれか1項記載の半導体デバイス。 - 半導体デバイスの製造方法において、前記方法は、
水平面に平行な第1主結晶方向(401)を有する結晶性半導体材料から成る半導体基板(502)に、長手方向に延在する長さが前記水平面における幅よりも長いトレンチ(150a)を形成するステップであって、前記トレンチ(150a)の長手方向軸(159a)を、前記水平面において最小で2°、最大で30°の傾斜角(φ)で、前記第1主結晶方向(401)に対し傾斜させるステップと、
前記半導体材料の原子が主結晶面に沿って再配列する温度まで、不活性雰囲気中で前記半導体基板(502)を加熱するステップであって、前記半導体材料の再堆積領域(191)によって、側壁段差(106)を形成し、前記側壁段差(106)によって、前記トレンチ(150a)の長手方向軸(159)と前記主結晶面との角度のずれを補償するステップと、
複数の前記再堆積領域(191)を一体化する犠牲層(192)を形成するステップと、
前記犠牲層(192)を除去するステップと、
前記トレンチ(150a)内にトレンチゲート構造(150)を形成するステップと、
を含む、
半導体デバイスの製造方法。 - 前記トレンチ(150a)を、±1°を超えない大きさでオフ角(α)から偏位したテーパ角(β)で先細りさせるステップをさらに含む、
請求項16記載の方法。 - 前記半導体基板(502)は、六方晶格子を有しており、前記第1主結晶方向(401)を、<11−20>結晶方向と<1−100>結晶方向のうちの一方とする、
請求項16または17記載の方法。 - 前記不活性雰囲気は、Ar,H2およびXeのうち少なくとも1つを含む、
請求項16から18のいずれか1項記載の方法。 - 前記不活性雰囲気は、炭化水素を含む、
請求項16から19のいずれか1項記載の方法。
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