JP6168686B2 - 熱に敏感な半導体デバイスの熱への露出を低減するための方法および構造体 - Google Patents

熱に敏感な半導体デバイスの熱への露出を低減するための方法および構造体 Download PDF

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JP6168686B2
JP6168686B2 JP2013114003A JP2013114003A JP6168686B2 JP 6168686 B2 JP6168686 B2 JP 6168686B2 JP 2013114003 A JP2013114003 A JP 2013114003A JP 2013114003 A JP2013114003 A JP 2013114003A JP 6168686 B2 JP6168686 B2 JP 6168686B2
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circuit
circuit board
tsv
tsvs
heat
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Japanese (ja)
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JP2013251545A (ja
JP2013251545A5 (https=
Inventor
ビー．マクシェーン マイケル
ビー．マクシェーン マイケル
ジェイ．ヘス ケビン
ジェイ．ヘス ケビン
エイチ．ペリー ペリー
エイチ．ペリー ペリー
エイ．スティーブンス タブ
エイ．スティーブンス タブ
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Memories (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2013114003A 2012-05-31 2013-05-30 熱に敏感な半導体デバイスの熱への露出を低減するための方法および構造体 Active JP6168686B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/485,886 US8680674B2 (en) 2012-05-31 2012-05-31 Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices
US13/485,886 2012-05-31

Publications (3)

Publication Number Publication Date
JP2013251545A JP2013251545A (ja) 2013-12-12
JP2013251545A5 JP2013251545A5 (https=) 2016-07-14
JP6168686B2 true JP6168686B2 (ja) 2017-07-26

Family

ID=49669203

Family Applications (1)

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JP2013114003A Active JP6168686B2 (ja) 2012-05-31 2013-05-30 熱に敏感な半導体デバイスの熱への露出を低減するための方法および構造体

Country Status (3)

Country Link
US (1) US8680674B2 (https=)
JP (1) JP6168686B2 (https=)
BR (1) BR102013013566B1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9093429B2 (en) 2012-06-27 2015-07-28 Freescale Semiconductor, Inc. Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices
US10319660B2 (en) * 2013-10-31 2019-06-11 Nxp Usa, Inc. Semiconductor device packages using a thermally enhanced conductive molding compound
WO2015103326A1 (en) * 2013-12-31 2015-07-09 Canon U.S. Life Sciences, Inc. Field deployable small format fast first result microfluidic system
US9184112B1 (en) 2014-12-17 2015-11-10 International Business Machines Corporation Cooling apparatus for an integrated circuit
US9472483B2 (en) 2014-12-17 2016-10-18 International Business Machines Corporation Integrated circuit cooling apparatus
CN108010931B (zh) * 2017-12-28 2021-03-30 苏州晶方半导体科技股份有限公司 一种光学指纹芯片的封装结构以及封装方法
US11276470B2 (en) * 2020-07-17 2022-03-15 Micron Technology, Inc. Bitline driver isolation from page buffer circuitry in memory device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0661382A (ja) * 1992-08-12 1994-03-04 Matsushita Electric Ind Co Ltd 半導体冷却装置
JPH08222700A (ja) * 1995-02-16 1996-08-30 Nissan Motor Co Ltd 半導体装置
US6190943B1 (en) 2000-06-08 2001-02-20 United Test Center Inc. Chip scale packaging method
TW497236B (en) 2001-08-27 2002-08-01 Chipmos Technologies Inc A soc packaging process
JP3791459B2 (ja) * 2002-05-27 2006-06-28 株式会社デンソー 半導体装置およびその製造方法
US7129640B2 (en) * 2003-06-03 2006-10-31 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Integrated circuit device for driving a laser diode with reduced heat transfer and method for fabricating the device
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
JP4458906B2 (ja) * 2004-04-05 2010-04-28 株式会社ルネサステクノロジ 半導体装置
JP4504798B2 (ja) * 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
US7339267B2 (en) 2005-05-26 2008-03-04 Freescale Semiconductor, Inc. Semiconductor package and method for forming the same
US7446407B2 (en) * 2005-08-31 2008-11-04 Chipmos Technologies Inc. Chip package structure
US7750459B2 (en) * 2008-02-01 2010-07-06 International Business Machines Corporation Integrated module for data processing system
US7935571B2 (en) 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US8604603B2 (en) * 2009-02-20 2013-12-10 The Hong Kong University Of Science And Technology Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers
JP2011249430A (ja) * 2010-05-24 2011-12-08 Panasonic Corp 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
BR102013013566B1 (pt) 2021-04-20
BR102013013566A2 (pt) 2015-10-20
JP2013251545A (ja) 2013-12-12
BR102013013566A8 (pt) 2017-10-10
US20130320480A1 (en) 2013-12-05
US8680674B2 (en) 2014-03-25

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