BR102013013566B1 - dispositivo semicondutor que usa vias através de silício cegas condutoras termicamente para a redução da exposição ao calor de dispositivos semicondutores sensíveis termicamente - Google Patents

dispositivo semicondutor que usa vias através de silício cegas condutoras termicamente para a redução da exposição ao calor de dispositivos semicondutores sensíveis termicamente Download PDF

Info

Publication number
BR102013013566B1
BR102013013566B1 BR102013013566-6A BR102013013566A BR102013013566B1 BR 102013013566 B1 BR102013013566 B1 BR 102013013566B1 BR 102013013566 A BR102013013566 A BR 102013013566A BR 102013013566 B1 BR102013013566 B1 BR 102013013566B1
Authority
BR
Brazil
Prior art keywords
circuit
tsvs
heat
semiconductor device
substrate
Prior art date
Application number
BR102013013566-6A
Other languages
English (en)
Portuguese (pt)
Other versions
BR102013013566A2 (pt
BR102013013566A8 (pt
Inventor
Michael B. Mcshane
Kevin J. Hess
Perry H. Pelley
Tab A. Stephens
Original Assignee
Nxp Usa, Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Usa, Inc filed Critical Nxp Usa, Inc
Publication of BR102013013566A2 publication Critical patent/BR102013013566A2/pt
Publication of BR102013013566A8 publication Critical patent/BR102013013566A8/pt
Publication of BR102013013566B1 publication Critical patent/BR102013013566B1/pt

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Memories (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
BR102013013566-6A 2012-05-31 2013-05-31 dispositivo semicondutor que usa vias através de silício cegas condutoras termicamente para a redução da exposição ao calor de dispositivos semicondutores sensíveis termicamente BR102013013566B1 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/485886 2012-05-31
US13/485,886 US8680674B2 (en) 2012-05-31 2012-05-31 Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

Publications (3)

Publication Number Publication Date
BR102013013566A2 BR102013013566A2 (pt) 2015-10-20
BR102013013566A8 BR102013013566A8 (pt) 2017-10-10
BR102013013566B1 true BR102013013566B1 (pt) 2021-04-20

Family

ID=49669203

Family Applications (1)

Application Number Title Priority Date Filing Date
BR102013013566-6A BR102013013566B1 (pt) 2012-05-31 2013-05-31 dispositivo semicondutor que usa vias através de silício cegas condutoras termicamente para a redução da exposição ao calor de dispositivos semicondutores sensíveis termicamente

Country Status (3)

Country Link
US (1) US8680674B2 (https=)
JP (1) JP6168686B2 (https=)
BR (1) BR102013013566B1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9093429B2 (en) 2012-06-27 2015-07-28 Freescale Semiconductor, Inc. Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices
US10319660B2 (en) * 2013-10-31 2019-06-11 Nxp Usa, Inc. Semiconductor device packages using a thermally enhanced conductive molding compound
WO2015103326A1 (en) * 2013-12-31 2015-07-09 Canon U.S. Life Sciences, Inc. Field deployable small format fast first result microfluidic system
US9184112B1 (en) 2014-12-17 2015-11-10 International Business Machines Corporation Cooling apparatus for an integrated circuit
US9472483B2 (en) 2014-12-17 2016-10-18 International Business Machines Corporation Integrated circuit cooling apparatus
CN108010931B (zh) * 2017-12-28 2021-03-30 苏州晶方半导体科技股份有限公司 一种光学指纹芯片的封装结构以及封装方法
US11276470B2 (en) * 2020-07-17 2022-03-15 Micron Technology, Inc. Bitline driver isolation from page buffer circuitry in memory device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0661382A (ja) * 1992-08-12 1994-03-04 Matsushita Electric Ind Co Ltd 半導体冷却装置
JPH08222700A (ja) * 1995-02-16 1996-08-30 Nissan Motor Co Ltd 半導体装置
US6190943B1 (en) 2000-06-08 2001-02-20 United Test Center Inc. Chip scale packaging method
TW497236B (en) 2001-08-27 2002-08-01 Chipmos Technologies Inc A soc packaging process
JP3791459B2 (ja) * 2002-05-27 2006-06-28 株式会社デンソー 半導体装置およびその製造方法
US7129640B2 (en) * 2003-06-03 2006-10-31 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Integrated circuit device for driving a laser diode with reduced heat transfer and method for fabricating the device
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
JP4458906B2 (ja) * 2004-04-05 2010-04-28 株式会社ルネサステクノロジ 半導体装置
JP4504798B2 (ja) * 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
US7339267B2 (en) 2005-05-26 2008-03-04 Freescale Semiconductor, Inc. Semiconductor package and method for forming the same
US7446407B2 (en) * 2005-08-31 2008-11-04 Chipmos Technologies Inc. Chip package structure
US7750459B2 (en) * 2008-02-01 2010-07-06 International Business Machines Corporation Integrated module for data processing system
US7935571B2 (en) 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US8604603B2 (en) * 2009-02-20 2013-12-10 The Hong Kong University Of Science And Technology Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers
JP2011249430A (ja) * 2010-05-24 2011-12-08 Panasonic Corp 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
JP6168686B2 (ja) 2017-07-26
BR102013013566A2 (pt) 2015-10-20
JP2013251545A (ja) 2013-12-12
BR102013013566A8 (pt) 2017-10-10
US20130320480A1 (en) 2013-12-05
US8680674B2 (en) 2014-03-25

Similar Documents

Publication Publication Date Title
BR102013013566B1 (pt) dispositivo semicondutor que usa vias através de silício cegas condutoras termicamente para a redução da exposição ao calor de dispositivos semicondutores sensíveis termicamente
JP6117787B2 (ja) Ｉｃパッケージ内へのｄｒａｍ及びｓｏｃのパッケージング
US7522421B2 (en) Split core circuit module
US9564417B2 (en) Multi-stacked structures of semiconductor packages
US8400807B2 (en) Semiconductor system
US9922962B2 (en) Cooling system for 3D IC
US11239133B2 (en) Apparatus and method for dissipating heat in multiple semiconductor device modules
KR101951082B1 (ko) 기판 어셈블리들을 위한 열 소산
US8350389B2 (en) Semiconductor device and information processing system including the same
US20110012255A1 (en) Semiconductor device
US7224059B2 (en) Method and apparatus for thermo-electric cooling
JP2021517294A5 (https=)
TWI879826B (zh) 電子封裝體及電子系統
KR102870424B1 (ko) 하이퍼칩
JP6007323B2 (ja) 異種メモリを混載したメモリモジュール、及びそれを搭載した情報処理装置
JP2011023587A5 (https=)
US11901349B2 (en) Semiconductor packages and methods for forming the same
US20190103290A1 (en) Thermal vapor chamber arrangement
US9093429B2 (en) Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices
US20090096086A1 (en) Cooling system for semiconductor devices
JP2013251545A5 (https=)
JPH1187574A (ja) 垂直実装形半導体チップパッケージ及びそれを含むパッケージモジュール
US20210144840A1 (en) Heat spreaders for semiconductor device modules
CN203774286U (zh) 一种带散热装置的pop封装
WO2025106123A1 (en) Hybrid bonded inverted memory-logic stack

Legal Events

Date Code Title Description
B03A Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]
B25A Requested transfer of rights approved

Owner name: NXP USA, INC. (US)

B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 31/05/2013, OBSERVADAS AS CONDICOES LEGAIS.