BR102013013566A8 - Dispositivo semicondutor que usa vias através de silício cegas condutoras termicamente para a redução da exposição ao calor de dispositivos semicondutores sensíveis termicamente - Google Patents

Dispositivo semicondutor que usa vias através de silício cegas condutoras termicamente para a redução da exposição ao calor de dispositivos semicondutores sensíveis termicamente

Info

Publication number
BR102013013566A8
BR102013013566A8 BR102013013566A BR102013013566A BR102013013566A8 BR 102013013566 A8 BR102013013566 A8 BR 102013013566A8 BR 102013013566 A BR102013013566 A BR 102013013566A BR 102013013566 A BR102013013566 A BR 102013013566A BR 102013013566 A8 BR102013013566 A8 BR 102013013566A8
Authority
BR
Brazil
Prior art keywords
semiconductor device
conductory
reducing heat
thermally sensitive
heat exposure
Prior art date
Application number
BR102013013566A
Other languages
English (en)
Other versions
BR102013013566A2 (pt
BR102013013566B1 (pt
Inventor
B Mcshane Michael
J Hess Kevin
H Pelley Perry
A Stephens Tab
Original Assignee
Freescale Semiconductor Inc
Nxp Usa Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Nxp Usa Inc filed Critical Freescale Semiconductor Inc
Publication of BR102013013566A2 publication Critical patent/BR102013013566A2/pt
Publication of BR102013013566A8 publication Critical patent/BR102013013566A8/pt
Publication of BR102013013566B1 publication Critical patent/BR102013013566B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

MÉTODOS E ESTRUTURAS PARA REDUZIR EXPOSIÇÃO DE CALOR DE DISPOSITIVOS SEMICONDUTORES SENSÍVEIS TERMICAMENTE. Um dispositivo semicondutor compreende uma matriz de circuito integrado (IC) tendo um lado de topo e um lado de trás. O substrato de circuito inclui um circuito de fonte de calor, um circuito sensível ao calor, um substrato de embalagem juntamente com o lado de topo do substrato de circuito, e uma pluralidade de vias através de silício (TSVs) condutoras termicamente formadas a partir do lado de trás do substrato circuito para perto, mas não através do lado de topo do substrato de circuito.
BR102013013566-6A 2012-05-31 2013-05-31 dispositivo semicondutor que usa vias através de silício cegas condutoras termicamente para a redução da exposição ao calor de dispositivos semicondutores sensíveis termicamente BR102013013566B1 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/485,886 US8680674B2 (en) 2012-05-31 2012-05-31 Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices
US13/485886 2012-05-31

Publications (3)

Publication Number Publication Date
BR102013013566A2 BR102013013566A2 (pt) 2015-10-20
BR102013013566A8 true BR102013013566A8 (pt) 2017-10-10
BR102013013566B1 BR102013013566B1 (pt) 2021-04-20

Family

ID=49669203

Family Applications (1)

Application Number Title Priority Date Filing Date
BR102013013566-6A BR102013013566B1 (pt) 2012-05-31 2013-05-31 dispositivo semicondutor que usa vias através de silício cegas condutoras termicamente para a redução da exposição ao calor de dispositivos semicondutores sensíveis termicamente

Country Status (3)

Country Link
US (1) US8680674B2 (pt)
JP (1) JP6168686B2 (pt)
BR (1) BR102013013566B1 (pt)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
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US9093429B2 (en) 2012-06-27 2015-07-28 Freescale Semiconductor, Inc. Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices
US10319660B2 (en) * 2013-10-31 2019-06-11 Nxp Usa, Inc. Semiconductor device packages using a thermally enhanced conductive molding compound
EP3089823A4 (en) * 2013-12-31 2017-12-20 Canon U.S. Life Sciences, Inc. Field deployable small format fast first result microfluidic system
US9472483B2 (en) 2014-12-17 2016-10-18 International Business Machines Corporation Integrated circuit cooling apparatus
US9184112B1 (en) 2014-12-17 2015-11-10 International Business Machines Corporation Cooling apparatus for an integrated circuit
CN108010931B (zh) * 2017-12-28 2021-03-30 苏州晶方半导体科技股份有限公司 一种光学指纹芯片的封装结构以及封装方法
US11276470B2 (en) * 2020-07-17 2022-03-15 Micron Technology, Inc. Bitline driver isolation from page buffer circuitry in memory device

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JPH0661382A (ja) * 1992-08-12 1994-03-04 Matsushita Electric Ind Co Ltd 半導体冷却装置
JPH08222700A (ja) * 1995-02-16 1996-08-30 Nissan Motor Co Ltd 半導体装置
US6190943B1 (en) 2000-06-08 2001-02-20 United Test Center Inc. Chip scale packaging method
TW497236B (en) 2001-08-27 2002-08-01 Chipmos Technologies Inc A soc packaging process
JP3791459B2 (ja) * 2002-05-27 2006-06-28 株式会社デンソー 半導体装置およびその製造方法
US7129640B2 (en) * 2003-06-03 2006-10-31 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Integrated circuit device for driving a laser diode with reduced heat transfer and method for fabricating the device
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
JP4458906B2 (ja) * 2004-04-05 2010-04-28 株式会社ルネサステクノロジ 半導体装置
JP4504798B2 (ja) * 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
US7339267B2 (en) 2005-05-26 2008-03-04 Freescale Semiconductor, Inc. Semiconductor package and method for forming the same
US7446407B2 (en) * 2005-08-31 2008-11-04 Chipmos Technologies Inc. Chip package structure
US7750459B2 (en) * 2008-02-01 2010-07-06 International Business Machines Corporation Integrated module for data processing system
US7935571B2 (en) 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US8604603B2 (en) * 2009-02-20 2013-12-10 The Hong Kong University Of Science And Technology Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers
JP2011249430A (ja) * 2010-05-24 2011-12-08 Panasonic Corp 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
JP6168686B2 (ja) 2017-07-26
US20130320480A1 (en) 2013-12-05
JP2013251545A (ja) 2013-12-12
BR102013013566A2 (pt) 2015-10-20
US8680674B2 (en) 2014-03-25
BR102013013566B1 (pt) 2021-04-20

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Legal Events

Date Code Title Description
B03A Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]
B25A Requested transfer of rights approved

Owner name: NXP USA, INC. (US)

B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 31/05/2013, OBSERVADAS AS CONDICOES LEGAIS.