JP6151340B2 - 化学機械研磨加工の間のインシトゥエッチングによる欠陥の除去 - Google Patents

化学機械研磨加工の間のインシトゥエッチングによる欠陥の除去 Download PDF

Info

Publication number
JP6151340B2
JP6151340B2 JP2015234383A JP2015234383A JP6151340B2 JP 6151340 B2 JP6151340 B2 JP 6151340B2 JP 2015234383 A JP2015234383 A JP 2015234383A JP 2015234383 A JP2015234383 A JP 2015234383A JP 6151340 B2 JP6151340 B2 JP 6151340B2
Authority
JP
Japan
Prior art keywords
slurry
protective layer
layer
cmp
planarization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015234383A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016129221A5 (https=
JP2016129221A (ja
Inventor
スコット ビー. シンジャー,
スコット ビー. シンジャー,
ジョセフ シー. ボワヴェール,
ジョセフ シー. ボワヴェール,
ダニエル シー. ロー,
ダニエル シー. ロー,
クリストファー エム. フェッツァー,
クリストファー エム. フェッツァー,
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing Co
Original Assignee
Boeing Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Boeing Co filed Critical Boeing Co
Publication of JP2016129221A publication Critical patent/JP2016129221A/ja
Publication of JP2016129221A5 publication Critical patent/JP2016129221A5/ja
Application granted granted Critical
Publication of JP6151340B2 publication Critical patent/JP6151340B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40Chemomechanical polishing [CMP]
    • H10P52/402Chemomechanical polishing [CMP] of semiconductor materials
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09GPOLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00Polishing compositions
    • C09G1/02Polishing compositions containing abrasives or grinding agents
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/60Wet etching
    • H10P50/64Wet etching of semiconductor materials
    • H10P50/642Chemical etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/60Wet etching
    • H10P50/64Wet etching of semiconductor materials
    • H10P50/642Chemical etching
    • H10P50/646Chemical etching of Group III-V materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/69Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/69Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/69Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/02Planarisation of semiconductor materials

Landscapes

  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
JP2015234383A 2014-12-01 2015-12-01 化学機械研磨加工の間のインシトゥエッチングによる欠陥の除去 Active JP6151340B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/556,337 2014-12-01
US14/556,337 US9431261B2 (en) 2014-12-01 2014-12-01 Removal of defects by in-situ etching during chemical-mechanical polishing processing

Publications (3)

Publication Number Publication Date
JP2016129221A JP2016129221A (ja) 2016-07-14
JP2016129221A5 JP2016129221A5 (https=) 2017-05-18
JP6151340B2 true JP6151340B2 (ja) 2017-06-21

Family

ID=54542064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015234383A Active JP6151340B2 (ja) 2014-12-01 2015-12-01 化学機械研磨加工の間のインシトゥエッチングによる欠陥の除去

Country Status (4)

Country Link
US (1) US9431261B2 (https=)
EP (2) EP4235751A3 (https=)
JP (1) JP6151340B2 (https=)
TW (1) TWI680508B (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN121013326A (zh) * 2024-05-22 2025-11-25 长鑫科技集团股份有限公司 半导体结构的制作方法以及半导体结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000031163A (ja) 1998-07-13 2000-01-28 Denso Corp 半導体装置及びその製造方法
KR100343136B1 (ko) * 1999-03-18 2002-07-05 윤종용 이중 연마저지층을 이용한 화학기계적 연마방법
US6417109B1 (en) * 2000-07-26 2002-07-09 Aiwa Co., Ltd. Chemical-mechanical etch (CME) method for patterned etching of a substrate surface
US7528075B2 (en) 2004-02-25 2009-05-05 Hrl Laboratories, Llc Self-masking defect removing method
JP4759298B2 (ja) * 2005-03-30 2011-08-31 株式会社フジミインコーポレーテッド 単結晶表面用の研磨剤及び研磨方法
DE102007019565A1 (de) 2007-04-25 2008-09-04 Siltronic Ag Verfahren zum einseitigen Polieren von Halbleiterscheiben und Halbleiterscheibe mit einer verspannt-relaxierten Si1-xGex-Schicht
WO2013018015A2 (en) 2011-08-01 2013-02-07 Basf Se A PROCESS FOR THE MANUFACTURE OF SEMICONDUCTOR DEVICES COMPRISING THE CHEMICAL MECHANICAL POLISHING OF ELEMENTAL GERMANIUM AND/OR Si1-XGeX MATERIAL IN THE PRESENCE OF A CMP COMPOSITION COMPRISING A SPECIFIC ORGANIC COMPOUND
JP6050934B2 (ja) 2011-11-08 2016-12-21 株式会社フジミインコーポレーテッド 研磨用組成物並びにそれを用いた研磨方法及び基板の製造方法
FR2994615A1 (fr) * 2012-08-14 2014-02-21 Commissariat Energie Atomique Procede de planarisation d'une couche epitaxiee

Also Published As

Publication number Publication date
EP4235751A2 (en) 2023-08-30
US20160155644A1 (en) 2016-06-02
US9431261B2 (en) 2016-08-30
JP2016129221A (ja) 2016-07-14
EP4235751A3 (en) 2023-11-15
TW201631652A (zh) 2016-09-01
TWI680508B (zh) 2019-12-21
EP3029717A1 (en) 2016-06-08

Similar Documents

Publication Publication Date Title
CN104752363B (zh) 快闪存储器的形成方法
JP5025508B2 (ja) ポリシリコン膜の除去方法および記憶媒体
JP5070196B2 (ja) エッチングプロセスのための安定化したフォトレジスト構成
US8440573B2 (en) Method and apparatus for pattern collapse free wet processing of semiconductor devices
JP5266496B2 (ja) 面取り基板のルーティング方法
US8304262B2 (en) Wiggling control for pseudo-hardmask
TWI666697B (zh) 基板處理方法、基板處理裝置及記憶媒體
CN101005025A (zh) 降低厚度变化的化学机械抛光方法及半导体器件制备方法
US20160035598A1 (en) Method for chemical planarization and chemical planarization apparatus
JP5015696B2 (ja) 半導体装置の製造方法及び製造装置
CN101197264B (zh) L型边墙的形成方法
JP6151340B2 (ja) 化学機械研磨加工の間のインシトゥエッチングによる欠陥の除去
CN102760653B (zh) 金属栅极的形成方法
CN104867826A (zh) 一种避免硅片边缘薄膜剥离的方法
CN102054665A (zh) 外延基片处理方法
CN101625999A (zh) Sonos存储器的制作方法
JP5047100B2 (ja) 使用済み半導体ウエハの再生方法
CN105374754B (zh) 半导体器件的制造方法
CN107658223A (zh) 一种闪存结构中多晶硅插塞的制备工艺
TW506008B (en) Semiconductor wafer manufacturing process
CN105304549A (zh) 浅沟槽隔离结构的形成方法
CN104795392B (zh) 一种阵列基板及其制备方法
CN104681496B (zh) 半导体结构的形成方法
CN108257885B (zh) 物理气相沉积中钛或氮化钛颗粒控片的使用方法
CN111066125A (zh) 蚀刻并机械研磨堆叠在半导体衬底上的膜层

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170321

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170321

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20170321

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20170417

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170425

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170524

R150 Certificate of patent or registration of utility model

Ref document number: 6151340

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250