JP6121497B2 - パッケージキャリアおよびその製造方法 - Google Patents
パッケージキャリアおよびその製造方法 Download PDFInfo
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- JP6121497B2 JP6121497B2 JP2015168459A JP2015168459A JP6121497B2 JP 6121497 B2 JP6121497 B2 JP 6121497B2 JP 2015168459 A JP2015168459 A JP 2015168459A JP 2015168459 A JP2015168459 A JP 2015168459A JP 6121497 B2 JP6121497 B2 JP 6121497B2
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- Prior art keywords
- solder resist
- layer
- carrier
- resist layer
- substrate
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims description 37
- 239000010410 layer Substances 0.000 claims description 233
- 229910000679 solder Inorganic materials 0.000 claims description 183
- 239000000463 material Substances 0.000 claims description 86
- 238000000059 patterning Methods 0.000 claims description 69
- 239000000758 substrate Substances 0.000 claims description 65
- 238000000034 method Methods 0.000 claims description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 29
- 239000011889 copper foil Substances 0.000 claims description 29
- 229920001187 thermosetting polymer Polymers 0.000 claims description 19
- 239000002335 surface treatment layer Substances 0.000 claims description 14
- 238000000016 photochemical curing Methods 0.000 claims description 12
- 238000010030 laminating Methods 0.000 claims description 7
- 239000000969 carrier Substances 0.000 claims 1
- 238000001723 curing Methods 0.000 description 6
- 239000003292 glue Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000013007 heat curing Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
- H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2439/00—Containers; Receptacles
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
110 キャリア
111 接続面
112 コア誘電体層
114 第1銅箔層
116 第2銅箔層
120 剥離型ソルダーレジスト層
120a ソルダーレジスト材料層
122a 突出部
130 基板
131 上表面
132 ベース
133 下表面
134 第1導電層
136 第2導電層
140a、140a’ 第1ソルダーレジスト材料層
140b、140b’ 第2ソルダーレジスト材料層
142a 第1パターニングソルダーレジスト層
142b 第2パターニングソルダーレジスト層
150a 第1表面処理層
150b 第2表面処理層
L、L’ 紫外線
T 加熱プロセス
Claims (16)
- 接続面を有するキャリアを提供するステップと、
前記キャリアの前記接続面に、前記接続面を完全に覆う剥離型ソルダーレジスト層を形成するステップと、
相対する上表面と下表面を有する基板を提供するステップと、
前記基板の前記下表面に、前記下表面の一部を露出する第1パターニングソルダーレジスト層を形成するステップと、
前記キャリアと前記基板をラミネートして、前記剥離型ソルダーレジスト層が、前記第1パターニングソルダーレジスト層に直接接触し、前記キャリアが、前記剥離型ソルダーレジスト層を介して前記第1パターニングソルダーレジスト層に仮接合されるステップと、
を含み、
前記剥離型ソルダーレジスト層を形成するステップが、
前記キャリアの前記接続面に熱硬化性ソルダーレジスト材料および光硬化性ソルダーレジスト材料を含むソルダーレジスト材料層を形成するステップと、
前記ソルダーレジスト材料層に対して光硬化プロセスを行い、前記剥離型ソルダーレジスト層を形成するステップと、
を含むパッケージキャリアの製造方法。 - 前記光硬化プロセスの照射エネルギーが、200mJ/cm2〜1600mJ/cm2である請求項1に記載のパッケージキャリアの製造方法。
- 前記第1パターニングソルダーレジスト層を形成する前記ステップが、
前記基板の前記下表面に、熱硬化性ソルダーレジスト材料および光硬化性ソルダーレジスト材料を含む第1ソルダーレジスト材料層を形成するステップと、
前記第1ソルダーレジスト材料層に対して光硬化プロセスおよび熱硬化プロセスを行い、前記第1ソルダーレジスト材料層を完全に硬化するステップと、
前記第1ソルダーレジスト材料層をパターニングして、前記第1パターニングソルダーレジスト層を形成するステップと、
を含む請求項1に記載のパッケージキャリアの製造方法。 - 前記基板の前記上表面に前記上表面の一部を露出する第2パターニングソルダーレジスト層を形成するステップ
をさらに含む請求項1に記載のパッケージキャリアの製造方法。 - 前記キャリアと前記基板をラミネートする前に、前記基板上に第1表面処理層および第2表面処理層を形成するステップ
をさらに含み、前記第1表面処理層が、前記第2パターニングソルダーレジスト層により露出した前記上表面の一部に配置され、前記第2表面処理層が、前記第1パターニングソルダーレジスト層により露出した前記下表面の一部に配置される請求項4に記載のパッケージキャリアの製造方法。 - 前記キャリアと前記基板をラミネートする温度が、90℃〜220℃である請求項1に記載のパッケージキャリアの製造方法。
- 前記キャリアが、コア誘電体層と、第1銅箔層と、第2銅箔層とを含み、前記第1銅箔層および前記第2銅箔層が、それぞれ、前記コア誘電体層の相対する両側に配置される請求項1に記載のパッケージキャリアの製造方法。
- 前記基板が、ベースと、第1導電層と、第2導電層とを含み、前記第1導電層および前記第2導電層が、それぞれ、前記ベースの相対する両側に配置される請求項1に記載のパッケージキャリアの製造方法。
- 前記キャリアと前記基板をラミネートする時、前記剥離型ソルダーレジスト層が、前記第1パターニングソルダーレジスト層に直接接触し、且つ前記第1パターニングソルダーレジスト層により露出した前記下表面の一部を覆う請求項1に記載のパッケージキャリアの製造方法。
- 接続面を有するキャリアと、
前記キャリアの前記接続面に配置され、且つ前記接続面を完全に覆う剥離型ソルダーレジスト層と、
相対する上表面と下表面を有する基板と、
前記基板の前記下表面に配置され、且つ前記下表面の一部を露出する第1パターニングソルダーレジスト層と、
を含み、前記キャリアが、前記剥離型ソルダーレジスト層を介して前記第1パターニングソルダーレジスト層に仮接合され、
前記剥離型ソルダーレジスト層の材料が、熱硬化性ソルダーレジスト材料および光硬化性ソルダーレジスト材料を含み、前記剥離型ソルダーレジスト層が、半硬化状態であるパッケージキャリア。 - 前記第1パターニングソルダーレジスト層の材料が、熱硬化性ソルダーレジスト材料および光硬化性ソルダーレジスト材料を含み、前記第1パターニングソルダーレジスト層が、完全な硬化状態である請求項10に記載のパッケージキャリア。
- 前記基板の前記上表面に配置され、且つ前記上表面の一部を露出する第2パターニングソルダーレジスト層
をさらに含む請求項10に記載のパッケージキャリア。 - 前記第2パターニングソルダーレジスト層の材料が、熱硬化性ソルダーレジスト材料および光硬化性ソルダーレジスト材料を含み、前記第2パターニングソルダーレジスト層が、完全な硬化状態である請求項12に記載のパッケージキャリア。
- 前記キャリアが、コア誘電体層と、第1銅箔層と、第2銅箔層とを含み、前記第1銅箔層および前記第2銅箔層が、それぞれ、前記コア誘電体層の相対する両側に配置される請求項10に記載のパッケージキャリア。
- 前記基板が、ベースと、第1導電層と、第2導電層とを含み、前記第1導電層および前記第2導電層が、それぞれ、前記ベースの相対する両側に配置される請求項10に記載のパッケージキャリア。
- 前記剥離型ソルダーレジスト層が、複数の突出部を含み、前記突出部が、前記第1パターニングソルダーレジスト層により露出した前記下表面の一部を覆う請求項10に記載のパッケージキャリア。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW104101087 | 2015-01-13 | ||
TW104101087A TWI586236B (zh) | 2015-01-13 | 2015-01-13 | 封裝載板及其製作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016131234A JP2016131234A (ja) | 2016-07-21 |
JP6121497B2 true JP6121497B2 (ja) | 2017-04-26 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015168459A Active JP6121497B2 (ja) | 2015-01-13 | 2015-08-28 | パッケージキャリアおよびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9668351B2 (ja) |
JP (1) | JP6121497B2 (ja) |
CN (1) | CN105990156B (ja) |
TW (1) | TWI586236B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210135111A (ko) | 2020-05-04 | 2021-11-12 | 삼성전자주식회사 | 반도체 패키지의 제조 방법 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5474958A (en) * | 1993-05-04 | 1995-12-12 | Motorola, Inc. | Method for making semiconductor device having no die supporting surface |
KR100674319B1 (ko) * | 2004-12-02 | 2007-01-24 | 삼성전기주식회사 | 얇은 코어층을 갖는 인쇄회로기판 제조방법 |
JP4933893B2 (ja) | 2006-12-28 | 2012-05-16 | パナソニック株式会社 | 熱プレス方法 |
JP5058929B2 (ja) | 2008-09-29 | 2012-10-24 | 京セラSlcテクノロジー株式会社 | 配線基板およびその製造方法 |
KR101627574B1 (ko) * | 2008-09-22 | 2016-06-21 | 쿄세라 코포레이션 | 배선 기판 및 그 제조 방법 |
KR20100043547A (ko) | 2008-10-20 | 2010-04-29 | 삼성전기주식회사 | 필드 비아 패드를 갖는 코어리스 기판 및 그 제조방법 |
JP2013522687A (ja) * | 2010-03-22 | 2013-06-13 | エルジー・ケム・リミテッド | 光硬化性及び熱硬化性を有する樹脂組成物、並びにドライフィルムソルダレジスト |
TWI429043B (zh) * | 2010-04-26 | 2014-03-01 | Advance Materials Corp | 電路板結構、封裝結構與製作電路板的方法 |
KR101140982B1 (ko) | 2010-09-07 | 2012-05-03 | 삼성전기주식회사 | 단층 인쇄회로기판 및 그 제조 방법 |
JP5625721B2 (ja) * | 2010-10-15 | 2014-11-19 | 日立化成株式会社 | 感光性樹脂組成物及びこれを用いた感光性エレメント |
TWI527173B (zh) * | 2013-10-01 | 2016-03-21 | 旭德科技股份有限公司 | 封裝載板 |
-
2015
- 2015-01-13 TW TW104101087A patent/TWI586236B/zh active
- 2015-03-02 CN CN201510092200.9A patent/CN105990156B/zh active Active
- 2015-04-15 US US14/686,785 patent/US9668351B2/en active Active
- 2015-08-28 JP JP2015168459A patent/JP6121497B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
CN105990156A (zh) | 2016-10-05 |
US20160204054A1 (en) | 2016-07-14 |
CN105990156B (zh) | 2018-09-28 |
US9668351B2 (en) | 2017-05-30 |
TWI586236B (zh) | 2017-06-01 |
JP2016131234A (ja) | 2016-07-21 |
TW201626871A (zh) | 2016-07-16 |
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