JP6094413B2 - 半導体モジュール及びその製造方法 - Google Patents
半導体モジュール及びその製造方法 Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
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- 239000004945 silicone rubber Substances 0.000 description 1
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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Description
図1は本発明の実施の形態1に係る半導体モジュールを示す斜視図である。図2は本発明の実施の形態1に係る半導体モジュールを示す断面図である。図3は本発明の実施の形態1に係る半導体モジュールの内部を示す斜視図である。
図12は、本発明の実施の形態2に係る半導体モジュールのベース板を示す平面図である。ベース板1上の半田レジスト4a,4bのパターン形状が実施の形態1とは異なり、その他の構成は実施の形態1と同様である。
図13は、本発明の実施の形態3に係る半導体モジュールのベース板を示す平面図である。ベース板1上の半田レジスト4a,4bのパターン形状が実施の形態1とは異なり、その他の構成は実施の形態1と同様である。
Claims (12)
- 半田接合部と、前記半田接合部を囲むケース接着部とを含む主面を有するベース板と、
前記主面において前記半田接合部と前記ケース接着部の間に設けられた半田レジストと、
前記半田接合部に半田により接合された半導体装置と、
前記ケース接着部に接着され、前記半導体装置を覆うケースとを備え、
前記半田レジストは、前記半田接合部の外周に沿って設けられた第1の半田レジストと、前記ケース接着部の内周に沿って設けられ、前記第1の半田レジストより外側に配置された第2の半田レジストとを有し、
前記主面を前記半田レジストから露出させるスリットが前記第1の半田レジストと前記第2の半田レジストの間に設けられ、
前記半田接合部は、第1及び第2の半田接合部を有し、
前記半導体装置は、前記第1及び第2の半田接合部にそれぞれ前記半田により接合された第1及び第2の半導体装置を有し、
前記第1の半導体装置と前記第2の半導体装置はワイヤにより互いに接続され、
前記スリットは、前記第1の半田接合部と前記第2の半田接合部の間にも設けられていることを特徴とする半導体モジュール。 - 前記スリットは前記半田接合部及び前記第1の半田レジストを囲んでいることを特徴とする請求項1に記載の半導体モジュール。
- 前記第1の半田レジストは、前記半田接合部の外周に沿って互いに離間して配置された複数のレジスト部を有し、
隣接する前記レジスト部の間の領域において前記主面が前記半田レジストから露出していることを特徴とする請求項1又は2に記載の半導体モジュール。 - 前記複数のレジスト部は、前記半田接合部のコーナー部に設けられていることを特徴とする請求項3に記載の半導体モジュール。
- 前記ケースの内部において前記半導体装置を覆う絶縁性ゲルを更に備えることを特徴とする請求項1〜4の何れか1項に記載の半導体モジュール。
- モジュール取付用のブッシュ穴が前記第2の半田レジストよりも外側において前記ベース板に設けられていることを特徴とする請求項1〜5の何れか1項に記載の半導体モジュール。
- 半田接合部と、前記半田接合部を囲むケース接着部とを含む主面を有するベース板を用意する工程と、
前記主面において前記半田接合部と前記ケース接着部の間に半田レジストを形成する工程と、
前記半田レジストを形成した後に、半導体装置を前記半田接合部に半田により接合する工程と、
前記半導体装置を覆うケースを前記ケース接着部に接着する工程とを備え、
前記半田レジストを形成する工程において、
前記半田接合部の外周に沿って第1の半田レジストを形成し、
前記ケース接着部の内周に沿って前記第1の半田レジストより外側に第2の半田レジストを形成し、
前記主面を前記半田レジストから露出させるスリットを前記第1の半田レジストと前記第2の半田レジストの間に形成し、
前記半田接合部として第1及び第2の半田接合部を形成し、
前記半導体装置として第1及び第2の半導体装置をそれぞれ前記第1及び第2の半田接合部に前記半田により接合し、
前記第1の半導体装置と前記第2の半導体装置をワイヤにより互いに接続し、
前記スリットを前記第1の半田接合部と前記第2の半田接合部の間にも形成することを特徴とする半導体モジュールの製造方法。 - 前記半田接合部及び前記第1の半田レジストを囲むように前記スリットを形成することを特徴とする請求項7に記載の半導体モジュールの製造方法。
- 前記第1の半田レジストとして、前記半田接合部の外周に沿って互いに離間して配置された複数のレジスト部を形成し、
隣接する前記レジスト部の間の領域において前記主面を前記半田レジストから露出させることを特徴とする請求項7又は8に記載の半導体モジュールの製造方法。 - 前記複数のレジスト部を前記半田接合部のコーナー部に形成することを特徴とする請求項9に記載の半導体モジュールの製造方法。
- 前記半導体装置を覆う絶縁性ゲルを前記ケースの内部に注入する工程を更に備えることを特徴とする請求項7〜10の何れか1項に記載の半導体モジュールの製造方法。
- モジュール取付用のブッシュ穴を前記第2の半田レジストよりも外側において前記ベース板に形成することを特徴とする請求項7〜11の何れか1項に記載の半導体モジュールの製造方法。
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DE112016006225B4 (de) * | 2016-01-14 | 2022-04-21 | Mitsubishi Electric Corporation | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung mit einer Abstrahlungsplattenstruktur |
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JP6907697B2 (ja) * | 2017-05-18 | 2021-07-21 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP6898203B2 (ja) * | 2017-10-27 | 2021-07-07 | 株式会社 日立パワーデバイス | パワー半導体モジュール |
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