JP6076268B2 - パイプラインａｄｃ内部ステージ誤差キャリブレーション - Google Patents

パイプラインａｄｃ内部ステージ誤差キャリブレーション Download PDF

Info

Publication number
JP6076268B2
JP6076268B2 JP2013555511A JP2013555511A JP6076268B2 JP 6076268 B2 JP6076268 B2 JP 6076268B2 JP 2013555511 A JP2013555511 A JP 2013555511A JP 2013555511 A JP2013555511 A JP 2013555511A JP 6076268 B2 JP6076268 B2 JP 6076268B2
Authority
JP
Japan
Prior art keywords
adc
coupled
stage
pipeline
stages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013555511A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014506773A5 (enExample
JP2014506773A (ja
Inventor
シー クン
シー クン
セストック チャールズ
セストック チャールズ
サターザデー パトリック
サターザデー パトリック
ジェイ レドファーン アーサー
ジェイ レドファーン アーサー
Original Assignee
日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本テキサス・インスツルメンツ株式会社, テキサス インスツルメンツ インコーポレイテッド, テキサス インスツルメンツ インコーポレイテッド filed Critical 日本テキサス・インスツルメンツ株式会社
Publication of JP2014506773A publication Critical patent/JP2014506773A/ja
Publication of JP2014506773A5 publication Critical patent/JP2014506773A5/ja
Application granted granted Critical
Publication of JP6076268B2 publication Critical patent/JP6076268B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
JP2013555511A 2011-02-22 2012-02-22 パイプラインａｄｃ内部ステージ誤差キャリブレーション Active JP6076268B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/032,457 US8451152B2 (en) 2011-02-22 2011-02-22 Pipelined ADC inter-stage error calibration
US13/032,457 2011-02-22
PCT/US2012/026022 WO2012116006A2 (en) 2011-02-22 2012-02-22 Pipelined adc inter-stage error calibration

Publications (3)

Publication Number Publication Date
JP2014506773A JP2014506773A (ja) 2014-03-17
JP2014506773A5 JP2014506773A5 (enExample) 2015-03-26
JP6076268B2 true JP6076268B2 (ja) 2017-02-08

Family

ID=46652285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013555511A Active JP6076268B2 (ja) 2011-02-22 2012-02-22 パイプラインａｄｃ内部ステージ誤差キャリブレーション

Country Status (4)

Country Link
US (1) US8451152B2 (enExample)
JP (1) JP6076268B2 (enExample)
CN (1) CN103392297B (enExample)
WO (1) WO2012116006A2 (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8368571B2 (en) * 2011-03-31 2013-02-05 Analog Devices, Inc. Pipelined ADC having error correction
US8358228B2 (en) * 2011-06-14 2013-01-22 Analog Devices, Inc. Method for modifying the LMS algorithm to reduce the effect of correlated perturbations
US8941518B2 (en) * 2012-02-14 2015-01-27 Hittite Microwave Corporation Methods and apparatus for calibrating pipeline analog-to-digital converters having multiple channels
US9231539B2 (en) * 2013-03-06 2016-01-05 Analog Devices Global Amplifier, a residue amplifier, and an ADC including a residue amplifier
US8836558B1 (en) * 2013-03-15 2014-09-16 Analog Devices, Inc. Method and device for improving convergence time in correlation-based algorithms
US9154146B1 (en) 2014-06-03 2015-10-06 The Board Of Regents, The University Of Texas System Dynamic offset injection for CMOS ADC front-end linearization
CN104300981B (zh) * 2014-09-30 2018-04-27 成都市晶林科技有限公司 高速、高精度图像信号模数转换电路
CN105897265B (zh) 2014-12-12 2020-08-21 恩智浦美国有限公司 具有受控误差校准的模数转换器
US9602121B2 (en) * 2015-07-07 2017-03-21 Analog Devices, Inc. Background estimation of comparator offset of an analog-to-digital converter
CN107453756B (zh) * 2017-08-17 2020-02-04 电子科技大学 一种用于流水线adc的前端校准方法
US10284188B1 (en) 2017-12-29 2019-05-07 Texas Instruments Incorporated Delay based comparator
US10673452B1 (en) 2018-12-12 2020-06-02 Texas Instruments Incorporated Analog-to-digital converter with interpolation
US10673456B1 (en) 2018-12-31 2020-06-02 Texas Instruments Incorporated Conversion and folding circuit for delay-based analog-to-digital converter system
US11316526B1 (en) 2020-12-18 2022-04-26 Texas Instruments Incorporated Piecewise calibration for highly non-linear multi-stage analog-to-digital converter
US11387840B1 (en) 2020-12-21 2022-07-12 Texas Instruments Incorporated Delay folding system and method
US11309903B1 (en) 2020-12-23 2022-04-19 Texas Instruments Incorporated Sampling network with dynamic voltage detector for delay output
US11438001B2 (en) 2020-12-24 2022-09-06 Texas Instruments Incorporated Gain mismatch correction for voltage-to-delay preamplifier array
US11962318B2 (en) 2021-01-12 2024-04-16 Texas Instruments Incorporated Calibration scheme for a non-linear ADC
CN112910462B (zh) * 2021-01-15 2023-02-21 迈科微电子(深圳)有限公司 一种基于亚稳态检测的pipeline-SAR ADC数字级间增益校准方法
US11316525B1 (en) 2021-01-26 2022-04-26 Texas Instruments Incorporated Lookup-table-based analog-to-digital converter
JP2024505551A (ja) 2021-02-01 2024-02-06 テキサス インスツルメンツ インコーポレイテッド 非線形システムのためのルックアップテーブル
US11881867B2 (en) 2021-02-01 2024-01-23 Texas Instruments Incorporated Calibration scheme for filling lookup table in an ADC
US12101096B2 (en) 2021-02-23 2024-09-24 Texas Instruments Incorporated Differential voltage-to-delay converter with improved CMRR
CN113098511B (zh) * 2021-03-01 2023-03-21 深圳市纽瑞芯科技有限公司 一种流水线逐次逼近型模数转换器的前端自校准方法
US12206424B2 (en) * 2022-08-30 2025-01-21 Texas Instruments Incorporated Methods and apparatus to reduce inter-stage gain errors in analog-to-digital converters

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081215A (en) 1998-07-06 2000-06-27 Motorola, Inc. High speed interlaced analog interface
US6445317B2 (en) 1998-11-20 2002-09-03 Telefonaktiebolaget L M Ericsson (Publ) Adaptively calibrating analog-to-digital conversion
JP4547064B2 (ja) 1999-03-24 2010-09-22 株式会社アドバンテスト Ａ／ｄ変換装置およびキャリブレーション装置
JP3865109B2 (ja) * 2000-02-21 2007-01-10 横河電機株式会社 オフセットミスマッチの校正方法及びこれを用いたａ／ｄ変換回路
EP1255357B1 (en) * 2001-05-02 2008-11-05 Texas Instruments Incorporated Correction of operational amplifier gain error in pipelined analog to digital converters
US6563445B1 (en) * 2001-11-28 2003-05-13 Analog Devices, Inc. Self-calibration methods and structures for pipelined analog-to-digital converters
DE10255354B3 (de) * 2002-11-27 2004-03-04 Infineon Technologies Ag A/D-Wandler mit minimiertem Umschaltfehler
US7312734B2 (en) 2005-02-07 2007-12-25 Analog Devices, Inc. Calibratable analog-to-digital converter system
US7280064B2 (en) * 2005-09-08 2007-10-09 Realtek Semiconductor Corp. Pipeline ADC with minimum overhead digital error correction
US7595748B2 (en) * 2007-07-23 2009-09-29 Mediatek Inc. Method of gain error calibration in a pipelined analog-to-digital converter or a cyclic analog-to-digital converter
US7554469B2 (en) * 2007-08-21 2009-06-30 Mediatek Inc. Method for gain error estimation in an analog-to-digital converter and module thereof
US7595744B2 (en) * 2007-11-27 2009-09-29 Texas Instruments Incorporated Correcting offset errors associated with a sub-ADC in pipeline analog to digital converters
JP2010035140A (ja) * 2008-07-03 2010-02-12 Nec Electronics Corp アナログデジタル変換器
CN101741385A (zh) * 2008-11-10 2010-06-16 承景科技股份有限公司 前后级解析度可调的共享运算放大器的模数转换器
US8106805B2 (en) * 2009-03-05 2012-01-31 Realtek Semiconductor Corp. Self-calibrating pipeline ADC and method thereof

Also Published As

Publication number Publication date
CN103392297B (zh) 2017-08-29
US8451152B2 (en) 2013-05-28
CN103392297A (zh) 2013-11-13
WO2012116006A2 (en) 2012-08-30
WO2012116006A3 (en) 2012-11-22
US20120212358A1 (en) 2012-08-23
JP2014506773A (ja) 2014-03-17

Similar Documents

Publication Publication Date Title
JP6076268B2 (ja) パイプラインａｄｃ内部ステージ誤差キャリブレーション
EP1131888B1 (en) Method of calibrating an analog-to-digital converter, and a calibration equipment
US8519875B2 (en) System and method for background calibration of time interleaved analog to digital converters
US9866230B2 (en) Method and apparatus for calibration of a time interleaved ADC
US8269657B2 (en) Background calibration of offsets in interleaved analog to digital converters
KR20180122367A (ko) 교대 비교기를 갖는 adc의 dc 오프셋 보정
US7602324B1 (en) A/D converter and method for converting analog signals into digital signals
JP2014506773A5 (enExample)
US20220131549A1 (en) Analog-to-digital converter system using reference analog-to-digital converter with sampling point shifting and associated calibration method
US20070176814A1 (en) Analog-to-digital Converter Using Lookahead Pipelined Architecture and Open-loop Residue Amplifiers
US7830287B1 (en) Analog to digital converter having digital correction logic that utilizes a dither signal to correct a digital code
CN108270442B (zh) 具有增大分辨率的第一级的模-数转换器
WO2011118370A1 (ja) 時間インターリーブ方式ａ／ｄ変換装置
US7570191B2 (en) Methods and systems for designing high resolution analog to digital converters
Chukwunweike et al. Advancing precision in pipeline analog-to-digital converters: Leveraging MATLAB for design and analysis in next-generation communication systems
JP2004128995A (ja) 信号変換方法とこの方法を利用可能な信号変換回路およびアナログ−デジタル変換回路
Ye et al. A 14-bit 200-MS/s time-interleaved ADC calibrated with LMS-FIR and interpolation filter
Peng et al. A Background Calibration Technology for Pipelined ADCs Using Sub-Range Code Bin Reshaping
CN111147077B (zh) 用于模拟数字转换器残余放大器的增益校准装置及方法
Pacheco et al. Design of a 10-bit 40 ms/s pipelined adc using 1.5-bit with current-mode reference shifting
Li et al. A fast and accurate calibration method for high-speed high-resolution pipeline ADC
Yan et al. A fast correlation based background digital calibration for pipelined ADCs
Xu et al. Digital background skew calibration for time-interleaved shared-front-end SHA-less pipelined ADCs
Tang et al. A digital nonlinearity correction technique for pipelined ADC's
孙可旭 et al. A fast combination calibration of foreground and background for pipelined ADCs

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20130822

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150203

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150203

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160315

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20160615

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20160812

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160914

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20161102

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161102

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20161129

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161129

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20161220

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170110

R150 Certificate of patent or registration of utility model

Ref document number: 6076268

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313117

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250