JP6049668B2 - 利用可能な並列性の量に従って1命令当たりのエネルギーを変化させるためのシステム - Google Patents
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Description
Claims (8)
- グラフィックス回路と、
モデムと、
ネットワークコントローラと、
メモリーコントローラと、
第1の組のコアおよび第2の組のコアを含む複数のコアと、
を備え、
前記複数のコアのそれぞれは、1または複数の実行ユニットと、キャッシュとを含み、
前記1または複数の実行ユニットの少なくとも1つは、前記複数のコアが動作中において選択的に無効とされることができ、
前記第1の組のコアは、前記第2の組のコアの性能レベルと異なる性能レベルで動作することができ、
前記第1の組のコアおよび前記第2の組のコアは、類似または同一の命令セットアーキテクチャをサポートし、
前記第2の組のコアの性能レベルは、前記第1の組のコアのクロック周波数とは異なる前記第2の組のコアのクロック周波数に少なくとも基づき、
実行中のスレッドの数に基づき、前記第1の組のコアに含まれる第1クロック周波数で同時に動作するコアの数と、前記第2の組のコアに含まれる前記第1クロック周波数とは異なる第2クロック周波数で同時に動作するコアの数とが定められる、システム。 - 前記第1の組のコアおよび前記第2の組のコアの間でスレッドをマイグレーションするスレッドマイグレーションロジックを更に備える、請求項1に記載のシステム。
- 前記複数のコアを含むプロセッサの電力消費の大きさと所望の電力消費との間の差の時間積分を求める積分回路と、
前記積分回路を用いたフィードバックループと、
前記フィードバックループよりも高速なフィードバック制御を可能にするクロックスロットル回路と、
をさらに備える請求項1または2に記載のシステム。 - トランスレーション・ルックアサイドバッファを更に備える、請求項1から3のいずれか一項に記載のシステム。
- 音声デバイスと、
メモリと、
データストレージデバイスと、
グラフィックス回路と、
モデムと、
ネットワークコントローラと、
メモリーコントローラと、
第1の組のコアおよび第2の組のコアを含む複数のコアと、
を備え、
前記複数のコアのそれぞれは、1または複数の実行ユニットと、キャッシュとを含み、
前記1または複数の実行ユニットの少なくとも1つは、前記複数のコアが動作中において選択的に無効とされることができ、
前記第1の組のコアは、前記第2の組のコアの性能レベルと異なる性能レベルで動作することができ、
前記第1の組のコアおよび前記第2の組のコアは、類似または同一の命令セットアーキテクチャをサポートし、
前記第2の組のコアの性能レベルは、前記第1の組のコアのクロック周波数とは異なる前記第2の組のコアのクロック周波数に少なくとも基づき、
実行中のスレッドの数に基づき、前記第1の組のコアに含まれる第1クロック周波数で同時に動作するコアの数と、前記第2の組のコアに含まれる前記第1クロック周波数とは異なる第2クロック周波数で同時に動作するコアの数とが定められる、システム。 - 前記第1の組のコアおよび前記第2の組のコアの間でスレッドをマイグレーションするスレッドマイグレーションロジックを更に備える、請求項5に記載のシステム。
- 前記複数のコアを含むプロセッサの電力消費の大きさと所望の電力消費との間の差の時間積分を求める積分回路と、
前記積分回路を用いたフィードバックループと、
前記フィードバックループよりも高速なフィードバック制御を可能にするクロックスロットル回路と、
をさらに備える請求項5または6に記載のシステム。 - トランスレーション・ルックアサイドバッファを更に備える、請求項5から7のいずれか一項に記載のシステム。
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US10/952,627 | 2004-09-28 | ||
US10/952,627 US7437581B2 (en) | 2004-09-28 | 2004-09-28 | Method and apparatus for varying energy per instruction according to the amount of available parallelism |
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JP2013123127A Division JP5709938B2 (ja) | 2004-09-28 | 2013-06-11 | プロセッサ、コンピュータシステム、および方法 |
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JP2015028810A JP2015028810A (ja) | 2015-02-12 |
JP6049668B2 true JP6049668B2 (ja) | 2016-12-21 |
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JP2009232857A Pending JP2010092483A (ja) | 2004-09-28 | 2009-10-06 | 利用可能な並列性の量に従って1命令当たりのエネルギーを変化させるための方法及び装置 |
JP2011123762A Active JP5465215B2 (ja) | 2004-09-28 | 2011-06-01 | 利用可能な並列性の量に従って1命令当たりのエネルギーを変化させるための方法及び装置 |
JP2013123127A Active JP5709938B2 (ja) | 2004-09-28 | 2013-06-11 | プロセッサ、コンピュータシステム、および方法 |
JP2014204987A Active JP6049668B2 (ja) | 2004-09-28 | 2014-10-03 | 利用可能な並列性の量に従って1命令当たりのエネルギーを変化させるためのシステム |
JP2015257488A Active JP6289444B2 (ja) | 2004-09-28 | 2015-12-28 | 利用可能な並列性の量に従って1命令当たりのエネルギーを変化させるための方法及び装置 |
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JP2009232857A Pending JP2010092483A (ja) | 2004-09-28 | 2009-10-06 | 利用可能な並列性の量に従って1命令当たりのエネルギーを変化させるための方法及び装置 |
JP2011123762A Active JP5465215B2 (ja) | 2004-09-28 | 2011-06-01 | 利用可能な並列性の量に従って1命令当たりのエネルギーを変化させるための方法及び装置 |
JP2013123127A Active JP5709938B2 (ja) | 2004-09-28 | 2013-06-11 | プロセッサ、コンピュータシステム、および方法 |
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JP (6) | JP4898687B2 (ja) |
KR (1) | KR100880060B1 (ja) |
CN (1) | CN100565426C (ja) |
TW (1) | TWI315847B (ja) |
WO (1) | WO2006037119A2 (ja) |
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JP2008513912A (ja) | 2008-05-01 |
JP4898687B2 (ja) | 2012-03-21 |
KR100880060B1 (ko) | 2009-01-22 |
JP5465215B2 (ja) | 2014-04-09 |
CN100565426C (zh) | 2009-12-02 |
JP2013218721A (ja) | 2013-10-24 |
CN101076770A (zh) | 2007-11-21 |
TWI315847B (en) | 2009-10-11 |
TW200632742A (en) | 2006-09-16 |
JP5709938B2 (ja) | 2015-04-30 |
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