JP6001475B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP6001475B2 JP6001475B2 JP2013039712A JP2013039712A JP6001475B2 JP 6001475 B2 JP6001475 B2 JP 6001475B2 JP 2013039712 A JP2013039712 A JP 2013039712A JP 2013039712 A JP2013039712 A JP 2013039712A JP 6001475 B2 JP6001475 B2 JP 6001475B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- mounting surface
- wiring board
- conductor
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
1a 貫通孔
2 配線導体
3 貫通導体
3P 導電ペースト
10 配線基板
10a 搭載面
E イメージセンサ素子
Claims (1)
- 熱硬化性樹脂成分を含む樹脂系絶縁材料から成る絶縁層と、金属箔から成る配線導体とが交互に複数層積層されているとともに、前記絶縁層を挟んで上下に位置する前記配線導体同士が、前記絶縁層を貫通する貫通孔内に充填された導電ペーストの硬化物から成る貫通導体で接続されており、上面にイメージセンサ素子が搭載される長方形の搭載面を有する配線基板であって、最上層の前記配線導体は、前記搭載面の長手方向の中央部に対応する領域での配置密度が前記搭載面の長手方向の両端部に対応する領域での配置密度よりも低くなっており、最上層の前記絶縁層における前記熱硬化性樹脂成分が最上層の前記配線導体の側面間に浸入して前記搭載面が凹面形状となっていることを特徴とする配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013039712A JP6001475B2 (ja) | 2013-02-28 | 2013-02-28 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013039712A JP6001475B2 (ja) | 2013-02-28 | 2013-02-28 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014168006A JP2014168006A (ja) | 2014-09-11 |
JP6001475B2 true JP6001475B2 (ja) | 2016-10-05 |
Family
ID=51617561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013039712A Active JP6001475B2 (ja) | 2013-02-28 | 2013-02-28 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP6001475B2 (ja) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3273670B2 (ja) * | 1993-08-31 | 2002-04-08 | 株式会社東芝 | 固体撮像装置 |
JP4632514B2 (ja) * | 2000-10-31 | 2011-02-16 | 京セラ株式会社 | 配線基板およびその製造方法 |
JP2009152282A (ja) * | 2007-12-19 | 2009-07-09 | Shinko Electric Ind Co Ltd | 集合配線基板及び半導体パッケージ |
-
2013
- 2013-02-28 JP JP2013039712A patent/JP6001475B2/ja active Active
Also Published As
Publication number | Publication date |
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JP2014168006A (ja) | 2014-09-11 |
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