JP5858600B2 - チップ実装方法 - Google Patents
チップ実装方法 Download PDFInfo
- Publication number
- JP5858600B2 JP5858600B2 JP2010145091A JP2010145091A JP5858600B2 JP 5858600 B2 JP5858600 B2 JP 5858600B2 JP 2010145091 A JP2010145091 A JP 2010145091A JP 2010145091 A JP2010145091 A JP 2010145091A JP 5858600 B2 JP5858600 B2 JP 5858600B2
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- substrate
- chip
- heating
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
前記基板の実装面に前記接着剤を塗布し、
前記基板の実装面に前記チップを配置して、第1の押圧力で前記バンプを前記基板に押圧し、
第1の加熱として、前記接着剤が硬化する硬化温度よりも低い予熱温度まで、前記接着剤を加熱し、
前記第1の押圧力よりも大きい第2の押圧力で、前記バンプを前記基板に押圧し、
その後、第2の加熱として、前記接着剤を前記硬化温度まで加熱するものであり、
前記予熱温度は、前記接着剤が完全には硬化しない範囲で、前記基板をできるだけ変形させるように設定され、
前記第2の押圧力は、前記バンプが前記基板の変形に追従して変形し前記基板に密着するように設定されており、
前記接着剤が200℃で10秒間加熱あるいは150℃で100秒間加熱することで硬化するものであり、前記第1の加熱において5秒程度で50℃から150℃に達するように加熱し、前記第2の加熱において200℃で10秒間加熱する、
ことを特徴とする。
2 接着剤
3 ICチップ(チップ)
4 スタッドバンプ(バンプ)
T ツール
Claims (1)
- 接合面にバンプが配設されたチップを、熱硬化性のエポキシ樹脂接着剤を介してガラス・エポキシ製の基板の上に実装するチップ実装方法であって、
前記基板の実装面に前記接着剤を塗布し、
前記基板の実装面に前記チップを配置して、第1の押圧力で前記バンプを前記基板に押圧し、
第1の加熱として、前記接着剤が硬化する硬化温度よりも低い予熱温度まで、前記接着剤を加熱し、
前記第1の押圧力よりも大きい第2の押圧力で、前記バンプを前記基板に押圧し、
その後、第2の加熱として、前記接着剤を前記硬化温度まで加熱するものであり、
前記予熱温度は、前記接着剤が完全には硬化しない範囲で、前記基板をできるだけ変形させるように設定され、
前記第2の押圧力は、前記バンプが前記基板の変形に追従して変形し前記基板に密着するように設定されており、
前記接着剤が200℃で10秒間加熱あるいは150℃で100秒間加熱することで硬化するものであり、前記第1の加熱において5秒程度で50℃から150℃に達するように加熱し、前記第2の加熱において200℃で10秒間加熱する、
ことを特徴とするチップ実装方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010145091A JP5858600B2 (ja) | 2010-06-25 | 2010-06-25 | チップ実装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010145091A JP5858600B2 (ja) | 2010-06-25 | 2010-06-25 | チップ実装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012009676A JP2012009676A (ja) | 2012-01-12 |
JP5858600B2 true JP5858600B2 (ja) | 2016-02-10 |
Family
ID=45539883
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010145091A Active JP5858600B2 (ja) | 2010-06-25 | 2010-06-25 | チップ実装方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5858600B2 (ja) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3270813B2 (ja) * | 1995-07-11 | 2002-04-02 | 株式会社ピーエフユー | 半導体装置とその製造方法 |
JPH11186325A (ja) * | 1997-12-24 | 1999-07-09 | Pfu Ltd | 半導体装置の製造方法 |
JP2002009111A (ja) * | 2000-06-21 | 2002-01-11 | Mitsui High Tec Inc | 半導体フリップ・チップの実装方法 |
JP3646056B2 (ja) * | 2000-11-06 | 2005-05-11 | 日本アビオニクス株式会社 | フリップチップ実装方法 |
JP2010040954A (ja) * | 2008-08-08 | 2010-02-18 | Furukawa Electric Co Ltd:The | 電子部品の製造方法 |
-
2010
- 2010-06-25 JP JP2010145091A patent/JP5858600B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2012009676A (ja) | 2012-01-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100384314B1 (ko) | 회로기판에의 전자부품 실장방법 및 장치 | |
JP4432949B2 (ja) | 電気部品の接続方法 | |
KR101398307B1 (ko) | 전기 부품의 실장 방법 및 실장 장치 | |
WO2010070806A1 (ja) | 半導体装置とフリップチップ実装方法およびフリップチップ実装装置 | |
JP2001313314A (ja) | バンプを用いた半導体装置、その製造方法、および、バンプの形成方法 | |
JP4659634B2 (ja) | フリップチップ実装方法 | |
KR101525158B1 (ko) | 인쇄회로기판 조립체 및 그 제조방법 | |
JP2009141267A (ja) | 電気部品の実装方法及び実装装置 | |
KR20100095031A (ko) | 전자부품 모듈의 제조 방법 | |
JP5228479B2 (ja) | 電子装置の製造方法 | |
JP5858600B2 (ja) | チップ実装方法 | |
KR20140031872A (ko) | 접속 구조체의 제조 방법 | |
JP2008235840A (ja) | 半導体装置の製造方法、半導体製造装置および半導体モジュール | |
JP2008210842A (ja) | バンプ付電子部品の実装方法 | |
JP2731383B2 (ja) | 部品実装構造及び部品実装方法 | |
JP2008192725A (ja) | 半導体装置及びその製造方法並びに半導体装置の製造装置 | |
CN100382265C (zh) | 配备凸块的电子元件的安装方法及其安装结构 | |
JP5451053B2 (ja) | フリップチップ実装方法とフリップチップ実装装置 | |
JP4767518B2 (ja) | 実装方法 | |
JP3419398B2 (ja) | 半導体装置の製造方法 | |
JP2010153670A (ja) | フリップチップ実装方法と半導体装置 | |
JP2004247621A (ja) | 半導体装置およびその製造方法 | |
JP2003204142A (ja) | 電子部品実装方法及び電子部品実装装置 | |
US20070194457A1 (en) | Semiconductor package featuring thin semiconductor substrate and liquid crystal polymer sheet, and method for manufacturing such semiconductor package | |
JP2012204717A (ja) | 電子機器、及び電子部品のリワーク方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130617 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140117 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140218 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140418 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20140418 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140610 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140807 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140902 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141126 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20141204 |
|
A912 | Removal of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20150109 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151016 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20151215 |
|
R150 | Certificate of patent (=grant) or registration of utility model |
Ref document number: 5858600 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |