JP5801030B2 - 浮遊ゲートメモリデバイスと製造 - Google Patents

浮遊ゲートメモリデバイスと製造 Download PDF

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JP5801030B2
JP5801030B2 JP2009516566A JP2009516566A JP5801030B2 JP 5801030 B2 JP5801030 B2 JP 5801030B2 JP 2009516566 A JP2009516566 A JP 2009516566A JP 2009516566 A JP2009516566 A JP 2009516566A JP 5801030 B2 JP5801030 B2 JP 5801030B2
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floating gate
gate
layer
memory
oxide
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Japanese (ja)
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JP2009541999A (ja
JP2009541999A5 (enExample
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誠一 有留
誠一 有留
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マイクロン テクノロジー， インク．
マイクロン テクノロジー， インク．
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP2009516566A 2006-06-21 2007-06-20 浮遊ゲートメモリデバイスと製造 Active JP5801030B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/471,772 2006-06-21
US11/471,772 US7977190B2 (en) 2006-06-21 2006-06-21 Memory devices having reduced interference between floating gates and methods of fabricating such devices
PCT/US2007/014431 WO2007149515A2 (en) 2006-06-21 2007-06-20 Floating gate memory devices and fabrication

Publications (3)

Publication Number Publication Date
JP2009541999A JP2009541999A (ja) 2009-11-26
JP2009541999A5 JP2009541999A5 (enExample) 2010-04-30
JP5801030B2 true JP5801030B2 (ja) 2015-10-28

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ID=38669533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009516566A Active JP5801030B2 (ja) 2006-06-21 2007-06-20 浮遊ゲートメモリデバイスと製造

Country Status (6)

Country Link
US (3) US7977190B2 (enExample)
EP (1) EP2036122A2 (enExample)
JP (1) JP5801030B2 (enExample)
KR (1) KR101350632B1 (enExample)
CN (1) CN101473429B (enExample)
WO (1) WO2007149515A2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7763933B2 (en) * 2007-02-15 2010-07-27 Micron Technology, Inc. Transistor constructions and processing methods
US7948021B2 (en) 2007-04-27 2011-05-24 Kabushiki Kaisha Toshiba Semiconductor memory device and method of fabricating the same
US20080273410A1 (en) * 2007-05-04 2008-11-06 Jaydeb Goswami Tungsten digitlines
JP4594973B2 (ja) 2007-09-26 2010-12-08 株式会社東芝 不揮発性半導体記憶装置
US8750040B2 (en) 2011-01-21 2014-06-10 Micron Technology, Inc. Memory devices having source lines directly coupled to body regions and methods
CN102184869B (zh) * 2011-04-28 2015-07-08 上海华虹宏力半导体制造有限公司 Mos晶体管隔离区制造方法及mos晶体管
CN105304549A (zh) * 2014-07-29 2016-02-03 盛美半导体设备（上海）有限公司 浅沟槽隔离结构的形成方法
EP3371812B1 (en) * 2015-11-03 2021-05-19 Silicon Storage Technology, Inc. Integration of metal floating gate in non-volatile memory

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781895B1 (en) * 1991-12-19 2004-08-24 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and memory system using the same
JP3469362B2 (ja) * 1994-08-31 2003-11-25 株式会社東芝 半導体記憶装置
US5622881A (en) * 1994-10-06 1997-04-22 International Business Machines Corporation Packing density for flash memories
JP3583579B2 (ja) 1997-06-06 2004-11-04 株式会社東芝 不揮発性半導体記憶装置およびその製造方法
JP4237344B2 (ja) * 1998-09-29 2009-03-11 株式会社東芝 半導体装置及びその製造方法
US6228713B1 (en) * 1999-06-28 2001-05-08 Chartered Semiconductor Manufacturing Ltd. Self-aligned floating gate for memory application using shallow trench isolation
US6461915B1 (en) * 1999-09-01 2002-10-08 Micron Technology, Inc. Method and structure for an improved floating gate memory cell
JP2002076272A (ja) * 2000-08-23 2002-03-15 Sony Corp 半導体装置の製造方法
JP3984020B2 (ja) * 2000-10-30 2007-09-26 株式会社東芝 不揮発性半導体記憶装置
US6656852B2 (en) * 2001-12-06 2003-12-02 Texas Instruments Incorporated Method for the selective removal of high-k dielectrics
US6795326B2 (en) * 2001-12-12 2004-09-21 Micron Technology, Inc. Flash array implementation with local and global bit lines
KR100462175B1 (ko) * 2002-02-08 2004-12-16 삼성전자주식회사 부유게이트를 갖는 비휘발성 메모리 소자의 셀 및 그제조방법
KR100537277B1 (ko) * 2002-11-27 2005-12-19 주식회사 하이닉스반도체 반도체 소자의 제조 방법
KR100501464B1 (ko) 2003-02-04 2005-07-18 동부아남반도체 주식회사 비휘발성 메모리 장치 제조 방법
JP4237561B2 (ja) 2003-07-04 2009-03-11 株式会社東芝 半導体記憶装置及びその製造方法
JP3923926B2 (ja) * 2003-07-04 2007-06-06 株式会社東芝 半導体記憶装置
JP3998622B2 (ja) 2003-09-30 2007-10-31 株式会社東芝 不揮発性半導体記憶装置およびその製造方法
US6982905B2 (en) * 2003-10-09 2006-01-03 Micron Technology, Inc. Method and apparatus for reading NAND flash memory array
US6996004B1 (en) * 2003-11-04 2006-02-07 Advanced Micro Devices, Inc. Minimization of FG-FG coupling in flash memory
KR20050048114A (ko) 2003-11-19 2005-05-24 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조 방법
US7045419B2 (en) * 2003-12-12 2006-05-16 Macronix International Co., Ltd. Elimination of the fast-erase phenomena in flash memory
JP2005209931A (ja) * 2004-01-23 2005-08-04 Renesas Technology Corp 不揮発性半導体記憶装置およびその製造方法
US6951790B1 (en) * 2004-03-24 2005-10-04 Micron Technology, Inc. Method of forming select lines for NAND memory devices
US7332408B2 (en) * 2004-06-28 2008-02-19 Micron Technology, Inc. Isolation trenches for memory devices
JP2007096151A (ja) * 2005-09-30 2007-04-12 Toshiba Corp 半導体記憶装置およびその製造方法

Also Published As

Publication number Publication date
WO2007149515A3 (en) 2008-02-21
US7977190B2 (en) 2011-07-12
EP2036122A2 (en) 2009-03-18
US8441058B2 (en) 2013-05-14
CN101473429B (zh) 2011-08-03
US20130237031A1 (en) 2013-09-12
US9018059B2 (en) 2015-04-28
JP2009541999A (ja) 2009-11-26
US20070296015A1 (en) 2007-12-27
KR20090034892A (ko) 2009-04-08
CN101473429A (zh) 2009-07-01
WO2007149515A2 (en) 2007-12-27
KR101350632B1 (ko) 2014-01-10
US20110266610A1 (en) 2011-11-03

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