JP5700241B2 - Multilayer wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer wiring board having a high density and smooth surface wiring pattern and excellent flip chip connectivity and wire bond connectivity and a method for manufacturing the same, and more particularly to a multilayer wiring substrate for a communication module.

  In recent years, along with downsizing, thinning, and high performance of mobile communication devices such as mobile phones, SAW (Surface Acoustic Wave) devices as high frequency filters are becoming smaller, thinner, and higher in frequency. . Along with this, in addition to increasing the density, the wiring board constituting the SAW device is also required to smooth the surface of the wiring pattern in order to ensure a filter function in reducing the thickness.

  As a conventional SAW device, a SAW piezoelectric element having a functional element region and an input / output electrode on one main surface side (active surface side) of the substrate, and one main surface side (active surface side) of the substrate on the wiring board side. For example, a SAW filter is formed by flip-chip mounting on a connection terminal face down (Patent Document 1). In addition, there is a type in which a SAW piezoelectric element is flip-chip mounted on a wiring board and provided with a blocking means provided for blocking the flow of the sealing resin on the active surface of the SAW piezoelectric element (Patent Document 2). .

  In addition, as a multilayer wiring board that meets the demand for higher density and thinner thickness, non-through vias are connected in a sequential structure over all layers (Patent Document 3), or non-through vias are formed over all layers. A multilayer wiring board having a so-called full stack structure in which a non-penetrating via is formed immediately above is proposed (Patent Documents 4 and 5).

Japanese Patent Laid-Open No. 11-097479 JP 2006-211612 A JP 2001-308548 A JP 2004-152915 A JP 2007-129180 A

  However, in the wiring substrate constituting the SAW device of Patent Documents 1 and 2, surface unevenness of the wiring pattern on the surface on which the SAW piezoelectric element is mounted is not considered. In recent years, with the increase in the frequency of mobile communication devices (for example, 0.45 to 4.0 GHz), the size and thickness of the SAW piezoelectric elements that are flip-chip connected in a face-down manner are increasing. There is a tendency that the vibration space formed in the gap between the vibration portion of the surface acoustic wave) and the wiring pattern on the surface of the wiring board is narrower (for example, about 10 μm). In such a case, if the surface irregularity of the wiring pattern on the surface of the wiring board on which the SAW piezoelectric element is mounted is large, there is a possibility that the wiring pattern and the active surface of the SAW piezoelectric element may come into contact with each other. there were.

  Further, in the wiring board constituting the SAW device of Patent Documents 1 and 2, the bump for connecting the flip chip of the SAW piezoelectric element is provided not on the interlayer connecting via of the wiring board but on a part of the wiring pattern. It is connected on the surface electrode. For this reason, when a resin wiring board is used, it is easy to soften by heat and pressure, so that the crimping force and ultrasonic waves at the time of flip chip connection are difficult to be transmitted to the connection location, and it is difficult to ensure connection reliability There is.

  In the multilayer wiring board having the sequential via structure of Patent Document 3, the inside of the non-through via is not filled with a metal such as plating. Therefore, the bump for flip chip connection of the SAW piezoelectric element is used as the interlayer connection via of the wiring board. It cannot be provided on top, but is connected to a surface layer electrode provided in a part of the wiring pattern on the insulating layer. For this reason, there is a problem that it is difficult to ensure the connection reliability because the crimping force and ultrasonic waves at the time of flip-chip connection are not easily transmitted to the connection location.

  Patent Document 4 A multilayer wiring board has a full stack via structure. However, it does not have a connection terminal for mounting an electronic component element directly above the filled via. Even if the bump for connecting the flip chip of the SAW piezoelectric element is provided on the via for connecting the interlayer of the wiring board, the via is filled with the conductive paste, so it is easy to be softened by heat or pressure. There is a problem that it is difficult to ensure the connection reliability because the crimping force and ultrasonic waves at the time of connection are not easily transmitted to the connection location.

  In the multilayer wiring board of Patent Document 5, a stacked structure in which vias are filled with plating metal and filled vias are stacked immediately above is possible. However, it does not have a connection terminal for mounting an electronic component element directly above the filled via. In addition, when a barrier metal layer is formed on the copper foil on the surface, and the plating at the time of interlayer connection is filled in the non-through holes, the interlayer connection is also formed on the copper foil on the surface on which the barrier metal layer is formed. A plating layer is formed by plating at that time, and then the plating on the barrier metal layer is removed to make only the copper foil. Therefore, even if the bumps for flip chip connection of the SAW piezoelectric element are provided on the vias for interlayer connection of the wiring board, the barrier metal layer is removed when the plating on the barrier metal layer of the copper foil on the surface is removed. Irregularities occur on the filled via surface where there is no gap. Therefore, the crimping force at the time of flip-chip mounting is not easily transmitted onto the surface terminals of the wiring board, and there is still a problem in connection reliability. The same applies to not only flip-chip connection but also wire bond connection.

  The present invention has been made in view of the above problems, and has a high density, excellent flip chip connectivity and wire bond connectivity, and ensures a filter function when used as a wiring board constituting a SAW device. An object of the present invention is to provide a multilayer wiring board and a method for manufacturing the same.

The present invention relates to the following.
1. A multilayer wiring board having an interlayer connection in which wiring patterns and insulating layers are alternately provided and connecting the wiring patterns through the insulating layer, wherein the interlayer connection is formed by filled vias formed by plating, A first layer wiring pattern is formed of a metal foil A disposed on the interlayer connection and connected to the back surface of the filled via by plating and the back surface , and a first insulating layer is formed on the inner layer side of the outermost first layer wiring pattern. The metal foil B and the plating for forming the second layer wiring pattern are arranged in this order, and the third layer wiring pattern is formed on the inner layer side of the second layer wiring pattern via the second insulating layer. metal foils C and plated are arranged in this order, the first insulating layer and the second insulating layer, a high Tg (glass transition temperature) material or a low alpha (thermal expansion coefficient) Zaidea Ru multilayer wiring board.
2. In 1 above, after forming the insulating layer, the wiring pattern, and the interlayer connection for connecting the respective wiring patterns only on one surface of the metal foil, the metal foil is subjected to circuit processing, whereby the outermost wiring pattern is formed. Is a multilayer wiring board formed of metal foil.
3. 3. The multilayer wiring board according to 1 or 2, wherein the interlayer connection formed by filled vias is provided in a substantially columnar shape over the entire thickness direction of the multilayer wiring board.
4). In any one of 1 to 3, the multilayer wiring board having nickel plating, nickel plating and gold plating, nickel plating, palladium plating and gold plating as protective plating on the outermost wiring pattern.
5. 5. The multilayer wiring board according to any one of 1 to 4, wherein the metal foil constituting the outermost wiring pattern is a copper foil having a thickness of 1 to 18 μm.
6). 5. The multilayer wiring board according to any one of 1 to 5, wherein the maximum roughness (Rz) of the surface of the protective plating formed on the outermost wiring pattern is less than 8 μm.
7). 7. The multilayer wiring board according to any one of 1 to 6, wherein the outermost wiring pattern located immediately above the interlayer connection forms a flip chip connection terminal or a wire bond connection terminal.
8). 8. An electronic device in which an electronic component element is mounted using a flip chip connection terminal or a wire bond connection terminal formed by the wiring pattern of the outermost layer of the multilayer wiring board according to 7 above.
9. 8. The electronic device according to 8, wherein a SAW piezoelectric element or PA element is mounted as an electronic component element to form a communication module.
10. A step (1) of preparing a metal foil A to be an outermost first layer conductor, and a step (2) of laminating a first insulating layer and a metal foil B to be a second layer conductor on the metal foil A; And (3) forming an interlayer connection hole from the second layer conductor to the first layer conductor in the first insulating layer, and the first layer conductor in the interlayer connection hole and on the second layer conductor. (4) performing filled via plating for electrically connecting the second layer conductor to the second layer conductor, and forming a second layer wiring pattern by circuit processing the second layer conductor after the filled via plating ( 5), the step (6) of repeating the steps (2) to (5) as many times as necessary on the second layer wiring pattern, and the circuit processing of the metal foil A which is the first layer conductor. By forming a layer wiring pattern, a connection end is formed immediately above the interlayer connection hole subjected to the filled via plating. Method for manufacturing a multilayer wiring board having the step (7), the forming the.
11. In 10 above, after processing the metal foil A, which is a first layer conductor, to form a first layer wiring pattern, a step of forming a connection terminal immediately above the interlayer connection hole subjected to filled via plating, A method of manufacturing a multilayer wiring board, wherein protective plating is formed on the connection terminal.
12 In 10 or 11 above, after preparing a core substrate having metal foils on both sides, and directly overlapping the metal foil A that is the first layer of the surface layer prepared in step (1) on the metal foil of the core substrate Steps (2) to (6) are performed, and then the step (9) of separating the plurality of wiring layers and the core substrate at the interface between the metal foil and the metal foil A of the core substrate, Forming a connection terminal directly above an interlayer connection hole subjected to filled via plating by processing a metal foil A as a layer conductor to form a first layer wiring pattern; A method for manufacturing a substrate.

  According to the present invention, a multilayer wiring board having high density, excellent flip-chip connectivity and wire bond connectivity, and capable of ensuring a filter function when used as a wiring board constituting a SAW device, and its A manufacturing method can be provided.

Sectional drawing of the communication module produced using the multilayer wiring board of this invention and this is shown. 1 is a cross-sectional view of a multilayer wiring board according to the present invention. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown.

  The multilayer wiring board of the present invention is a board for mounting electronic component elements. In the present invention, an electronic component element is a surface-mount type electronic component that is connected to a connection terminal on a wiring board by flip-chip connection or wire bond connection, such as a semiconductor element, SAW piezoelectric element, or PA (power amplifier) element. Refers to an element. There is no particular limitation as long as the electronic component element is mounted by flip chip connection or wire bond connection. For example, a SAW piezoelectric element or PA (power amplifier) element is mounted, so-called SAW filter package or PA module. As a member for forming a communication module such as a mobile phone, it is preferably used for a bare chip mounting application mainly in a communication module such as a mobile phone.

  An embodiment of the multilayer wiring board of the present invention is a multilayer wiring board in which wiring patterns and insulating layers are provided alternately, and has an interlayer connection that penetrates the insulating layers and connects the wiring patterns. A multilayer wiring board in which the first layer wiring pattern is formed of metal foil among the wiring patterns in which the connection is formed by filled vias by plating and is located immediately above the interlayer connection formed by the filled vias is exemplified. That is, there is a multilayer wiring board in which the first layer wiring pattern, which is the outermost layer wiring pattern, is arranged so as to cover the interlayer connection and is formed by a metal foil in which a filled via by plating and a back surface are directly connected.

  More specifically, an embodiment of the multilayer wiring board according to the present invention is shown in FIG. 1 and FIG. 2, in which a first layer wiring pattern 8 including a flip chip connection terminal 5 on one surface is replaced with a first insulating layer. The first filled via 10 formed in 9 is used as an interlayer connection, and has a wiring structure electrically connected to the second layer wiring pattern 11, and further the second filled via 13 formed in the second insulating layer 12 is connected as an interlayer connection. As a fourth layer including a portion to be the back electrode 7 with the third filled via 16 formed in the third insulating layer 15 as an interlayer connection. A multilayer wiring board 1 having a wiring structure electrically connected to a wiring pattern 17, wherein the first layer wiring pattern 8 is composed of a metal foil A 19, and a protective plating 22 is provided thereon. Filled Via 1 Immediately above, and it is a multi-layer wiring board 1 is flip-chip connection terminal 5 for mounting the electronic component element 3 is provided.

  That is, in the form shown in FIG. 1 and FIG. 2, it is the multilayer wiring board 1 having the flip chip connection terminal 5 on one surface and the back electrode 7 on the other surface, and the flip chip connection terminal 5 is an interlayer connection. Provided immediately above the filled vias 10, 13, 16, these filled vias 10, 13, 16 are provided immediately above the entire thickness direction of the multilayer wiring board 1, and are connected to the back electrode 7. The substrate 1 is used. On the front surface side (first layer side) of the multilayer wiring board 1, a flip chip connection terminal 5 for connecting the electronic component element 3 with the bump 4 is provided immediately above the first filled via 10. Reference numeral 3 denotes a bump 4 which is fixed and mounted on the multilayer wiring board 1.

  For this reason, in the form shown in FIGS. 1 and 2, the bump 4, the flip chip connection terminal 5, and the back electrode 7 are connected in the thickness direction of the multilayer wiring board 1 with interlayer connection (first filled via 10, second filled via 13, Since they are connected in a continuous state via the third filled via 16), a structure in which heat, pressure, and ultrasonic vibration when the electronic component element 3 is mounted is easily transmitted. In addition, the first layer wiring pattern 8 including the portion that becomes the flip chip connection terminal 5 is composed of only the metal foil A19, and filled via plating 21a, 21b is formed on the upper portion of the first wiring pattern 8 when the interlayer connection is formed by filled via plating. 21c are not formed. For this reason, the surface roughness and unevenness | corrugation of metal foil A19 do not expand by the plating layer 31 produced in the case of such an interlayer connection. Here, the plated layer 31 generated in the interlayer connection is, for example, in the conformal method, when filled via plating for interlayer connection is performed in the via, filled via plating is also formed on the metal foil on the surface, Although the thickness of the conductor on the surface increases, it means filled via plating formed on the metal foil at this time. Further, since the thickness of the first layer conductor 30 (shown in FIG. 4) composed of the metal foil A19 is not increased by the plating layer 31 generated at the time of interlayer connection, even when a fine pattern is formed, The metal foil A19 having a thickness corresponding to that can be selected, and it is not necessary to perform half etching or buffing, so that the surface roughness of the metal foil A19 does not increase. Therefore, the surface smoothness of the metal foil A19 can be used almost as it is, and the first layer wiring pattern 8 having excellent surface smoothness can be formed. Even when the protective plating 22 is formed on the first layer wiring pattern including the portion to become the flip chip connection terminal 5, the surface of the first layer wiring pattern 8 is smooth, so the surface of the protective plating 22 formed thereon Can also maintain smoothness. For this reason, since the flip chip connection terminal 5 excellent in surface smoothness can be formed, the multilayer wiring board 1 excellent in flip chip connection can be provided. Moreover, when the flip chip connection terminal 5 is formed as a wire bond connection terminal, the multilayer wiring board 1 excellent in wire bond connectivity can be provided. Here, half-etching means a process for facilitating fine circuit processing by reducing the conductor thickness by etching before forming a wiring pattern by circuit processing. By selecting the metal foil A19 to be used, the surface roughness of the protective plating 22 on the first layer wiring pattern 8 can also obtain a surface smoothness of less than 8 μm in terms of the maximum roughness (Rz). Here, the maximum roughness (Rz) is the maximum roughness (Rz) defined by JIS B 0601 (2001), and can be measured using a stylus type surface roughness meter or the like.

  Furthermore, in the form shown in FIGS. 1 and 2, the surface of the protective plating 22 on the first layer wiring pattern 8 similarly has smoothness other than the portion that becomes the flip chip connection terminal 5. For this reason, even when the SAW piezoelectric element 3 is mounted as the electronic component element 3, even when the first layer wiring pattern 8 is formed in a region below the active surface 39 (vibration portion of the surface acoustic wave) of the SAW piezoelectric element 3. The filter function of the SAW piezoelectric element 3 can be ensured. For example, in a SAW device used in a high frequency region of 0.45 to 4.0 GHz, the lower surface (active surface 39) of the SAW piezoelectric element 3 mounted on the multilayer wiring board 1 and the multilayer wiring are required in order to reduce the size and thickness. In some cases, the gap (vibration space) provided between the substrate 1 and the protective plating 22 on the first layer wiring pattern 8 is designed to be about 10 μm. For this reason, when the surface unevenness of the protective plating 22 on the first layer wiring pattern 8 on the surface on which the SAW piezoelectric element 3 is mounted is close to 10 μm or more, the protective plating 22 on the first layer wiring pattern 8 The SAW piezoelectric element 3 may be electrically connected, and does not function as a filter. Therefore, if the maximum roughness (Rz) of the protective plating 22 on the first layer wiring pattern 8 is adjusted so as to have a surface smoothness of less than 8 μm, a high-frequency SAW filter of about 0.45 to 4.0 GHz is used. When used as a substrate, it is effective to ensure the filter function.

  In the form shown in FIGS. 1 and 2, the first layer wiring pattern 8 can be formed only by processing the metal foil A19 by etching or the like. Therefore, if the thin metal foil A19 is used, the wiring pattern height increases. Densification can be achieved. Furthermore, the first layer wiring pattern 8 is not provided with a filled plating layer used for forming an interlayer connection on the upper portion thereof, so even when a fine wiring pattern is formed, so-called half etching, buffing, etc. Since a step of reducing the conductor thickness is not required, the number of steps is not increased, and the inexpensive multilayer wiring board 1 can be provided. In addition, when half etching or buffing is performed, the surface roughness of the conductor increases, so that these steps are unnecessary, not only reducing the number of steps, but also the first layer wiring pattern 8 and the protective plating thereon. 22 has the effect of maintaining the surface smoothness of the surface. As described above, according to the present invention, the multilayer wiring board suitable for the electronic component element 3 mounting application, in which the surface smoothness of the protective plating 22 on the first layer wiring pattern 8 including the flip chip connection terminal 5 is particularly required. 1 can be provided.

  The multilayer wiring board of the present invention is a board on which electronic component elements are mounted. For example, a SAW piezoelectric element or a PA (power amplifier) element is mounted to form a communication module such as a so-called SAW filter package or PA module. It can be used as a member. It is mainly used for bare chip mounting applications in communication modules such as mobile phones. The first layer wiring pattern of the present invention has a high density, and the protective plating formed thereon has a smooth surface. This is desirable because it can be done.

  In the present invention, the conductor means a metal foil having only a metal foil or a metal foil provided on the surface of an insulating layer and having a plating layer formed at the time of interlayer connection on the top, in a state before circuit processing. The wiring pattern means a pattern in which wiring and connection terminals are formed by processing this conductor, and does not include, for example, a pattern in which an opening for a conformal mask is provided. The plating layer generated at the time of interlayer connection is, for example, when filled via plating for interlayer connection is performed in the via in the conformal method, filled via plating is also formed on the metal foil on the surface, and the surface conductor Although the thickness increases, it means filled via plating formed on the metal foil at this time. Further, the first layer wiring pattern refers to a wiring pattern provided on the surface layer (first layer) on the side having a connection terminal with the electronic component element among the above wiring patterns. The wiring pattern of each layer is formed so as to include a position immediately above the interlayer connection formed by filled vias.

  Of the wiring patterns located immediately above the interlayer connection formed by filled vias, the first layer wiring pattern is formed of metal foil A. That is, in the first layer wiring pattern, the plating layer generated at the time of interlayer connection is not formed on the upper part of the metal foil A before circuit processing, the metal foil A is exposed, and only the metal foil A is the first. A layer conductor is formed, and the first layer wiring pattern is formed by circuit processing of the first layer conductor. For this reason, the first layer wiring pattern can use the surface smoothness of the metal foil A almost as it is, and can have excellent surface smoothness. For this reason, the surface of the protective plating formed on the first layer wiring pattern is also smoothed. In addition, since the first layer wiring pattern is processed by etching only the metal foil A, the conductor thickness is thin, so that a fine wiring pattern can be formed. For this reason, the process of reducing the conductor thickness by half etching, buffing or the like before the circuit processing is unnecessary.

  As a circuit processing method for the wiring patterns of each layer excluding the first layer wiring pattern, a circuit forming method used for a general electronic component element mounting substrate can be used. Examples of such a circuit forming method include a subtractive method and a semi-additive method.

  As the metal foil A used in the present invention, those used for a general electronic component element mounting substrate can be used, and a copper foil is particularly desirable from the viewpoint of electrical characteristics, circuit workability, and the like. Moreover, as for the surface roughness of copper foil, what has the surface smoothness of less than 8 micrometers in the maximum roughness (Rz) is desirable. If such a copper foil is used, the surface of the obtained wiring pattern can be made to have a maximum roughness (Rz) of less than 8 μm by processing the circuit so as to maintain the surface roughness of the copper foil. Furthermore, even when protective plating is formed on the wiring pattern, the surface of the protective plating can maintain smoothness equivalent to the surface roughness of the copper foil. Examples of such a copper foil include 3EC-VLP-12 (trade name, manufactured by Mitsui Kinzoku Mining Co., Ltd.). In addition, the metal foil may be replaced with a metal foil made of aluminum, brass, nickel, iron or the like alone, an alloy or a composite foil, or a copper foil plated or evaporated with a metal such as aluminum, nickel, silver, or gold. it can.

  In the present invention, the interlayer connection means that the wiring patterns of each layer are electrically connected to each other through an interlayer connection hole provided in the insulating layer, and is formed by so-called filled via plating. Examples of the filled via plating include filled via plating using electrolytic copper plating used for a general electronic component element mounting substrate.

  The filled via described in the present invention is an interlayer connection formed by filled via plating, and the inside of the interlayer connection hole is filled with a metal formed by filled via plating. The filled via can be formed by processing the insulating layer with a laser or the like to form an interlayer connection hole having a diameter of about 1 μm to 300 μm and then filling the interlayer connection hole with filled via plating.

  The insulating layer used in the present invention is intended to electrically insulate the wiring patterns in the respective layers and in the same layer, and also serves as a support for the wiring patterns of the respective layers by bonding the conductors of the respective layers. . The general thing used in manufacture of the board | substrate for a general electronic component element mounting can be used. For example, a thermosetting resin prepreg, a material mainly composed of a high molecular weight epoxy resin, or a thermosetting liquid or sheet insulating layer mainly composed of BT resin can be used. Thermosetting resin prepregs include GEA-679FG (trade name, manufactured by Hitachi Chemical Co., Ltd.) mainly composed of high molecular weight epoxy resin and GHPL-830NX Type A (Mitsubishi Gas Chemical Co., Ltd.) mainly composed of BT resin. Product name, SFX513 (manufactured by Shin-Etsu Chemical Co., Ltd., product name) and the like, and AS-3000 and AS2600W (both manufactured by Hitachi Chemical Co., Ltd.) as the sheet-like adhesive. ) (Trade name), high-performance adhesive sheet for electronic parts TAS (trade name, manufactured by Toray Industries, Inc.) and the like, but are not limited thereto. One type of insulating layer may be used alone, or two or more types of insulating layers may be stacked, and liquid types may be mixed and used.

  The insulating layer used in the present invention is more preferably a high Tg (glass transition point) / low α (thermal expansion coefficient) material. This prevents the connection terminal from sinking due to softening of the insulating layer due to high-temperature heating (for example, 230 ° C.) during electronic component element mounting (bump connection or wire bond connection), thereby reducing connection reliability. Can do. Here, the high Tg / low α material has a Tg point of 160 to 280 ° C. (TMA method: thermomechanical analysis method) and a thermal expansion coefficient of 120 to 180 ppm / ° C. (thickness direction of Tg point or more). An insulating layer is referred to. As such a high Tg / low α material, for example, an insulating layer in which an epoxy resin is filled with an inorganic filler can be used.

  Only on one surface of the metal foil A, an insulating layer, a wiring pattern, and an interlayer connection for connecting the respective wiring patterns are stacked and formed, and the first layer wiring pattern as the outermost wiring pattern is the metal foil A. Is formed by circuit processing. That is, multilayering is performed only on one surface of the metal foil A, and circuit processing is performed on the other surface of the metal foil A as it is without multilayering. On the other surface of the metal foil A, no insulating layer or wiring pattern is formed, and the initial surface state of the metal foil A is maintained. By processing this metal foil A, the first layer wiring pattern is formed of the metal foil A among the wiring patterns located immediately above the interlayer connection. Thereby, the 1st layer wiring pattern can use the surface smoothness of metal foil A as it is, and can be provided with the outstanding surface smoothness. For this reason, the surface smoothness of the protective plating formed on the first layer wiring pattern is also excellent. In addition, since the first layer wiring pattern is processed by etching only the metal foil A, the conductor thickness is thin, so that a fine wiring pattern can be formed. For this reason, the process of reducing the conductor thickness by half etching, buffing or the like before the circuit processing is unnecessary.

  It is desirable that the interlayer connection formed by filled vias has a full stack structure provided immediately above the entire thickness direction of the multilayer wiring board. That is, it is desirable that the interlayer connection formed by filled vias be provided in a substantially column shape over the entire thickness direction of the multilayer wiring board. As a result, filled vias filled with metal are stacked over the entire thickness direction of the multilayer wiring board. Therefore, if a connection terminal is provided immediately above the filled via, flip chip connection or wire is provided on the connection terminal. Heat, pressure, and ultrasonic vibration during bond connection are easily transmitted. For this reason, the multilayer wiring board excellent in flip chip connectivity and wire bond connectivity can be provided.

  It is desirable to have nickel plating or nickel plating and gold plating as protective plating on the first layer wiring pattern including the portion to be the connection terminal. It is more desirable to perform gold plating after performing palladium plating on nickel plating in terms of improving the connection reliability with the electronic component element. Silver plating may be used instead of gold plating. As these plating methods, electroless plating, electroplating, or displacement plating used for an electronic component element mounting substrate can be used. In addition, protective plating means the plating layer provided in the upper part of the wiring pattern after circuit formation, in order to protect a wiring pattern and to provide flip chip connectivity and wire bond connectivity.

  The metal foil A constituting the first layer wiring pattern is desirably a copper foil having a thickness of 1 to 18 μm. In the multilayer wiring board of the present invention, since the first layer wiring pattern is formed by processing the metal foil A, an appropriate thickness of the metal foil A can be selected, but the metal foil A has a thickness of 1 With a copper foil of ˜18 μm, for example, it is easy to form a high-density wiring pattern with a line / space of 30 μm / 30 μm or less.

  The metal foil A constituting the first layer wiring pattern preferably has a maximum surface roughness (Rz) of less than 8 μm. As a result, the metal foil A is subjected to circuit processing while maintaining the original surface roughness and becomes the first layer wiring pattern, so that the maximum roughness (Rz) of the surface of the first layer wiring pattern is less than 8 μm. be able to. Also, the surface roughness of the protective plating formed on the first layer wiring pattern can be maintained equally. Here, the maximum roughness (Rz) is the maximum roughness (Rz) defined by JIS B 0601 (2001), and can be measured using a stylus type surface roughness meter or the like.

  It is desirable that the first layer wiring pattern located immediately above the interlayer connection forms a flip chip connection terminal or a wire bond connection terminal. In the multilayer wiring board of the present invention, since the first layer wiring pattern is formed by processing the metal foil A, the surface state of the metal foil A is maintained, so that the surface smoothness of the metal foil A is maintained as it is. Can be used. For this reason, since the wiring pattern formed with this metal foil A is formed as a flip chip connection terminal or a wire bond connection terminal, the surface smoothness of the protective plating formed on the wiring pattern is excellent. It is possible to provide a multilayer wiring board having excellent properties and wire bond connectivity.

  In the present invention, the connection terminal is a terminal for making an electrical connection with the electronic component element by bumps or wire bonds, similar to those used in a general electronic component element mounting substrate. The connection terminal is formed by covering the surface of the first layer wiring pattern formed of the metal foil A with a protective plating such as gold or silver, so that workability and reliability when connecting with bumps, wire bonds, or solder are used. It is preferable in nature.

  The protective plating surface provided on the upper part of the connection terminal is preferably gold plating. Thereby, when using a gold bump as a bump used for flip chip connection, the connection between the connection terminal and the bump can be strengthened. Similarly, when a gold wire is used for wire bond connection, the connection between the connection terminal and the gold wire can be strengthened. Furthermore, solder wettability at the time of soldering can be ensured. Moreover, it is desirable to provide nickel plating as a base for gold plating, and it is desirable to perform gold plating after providing palladium plating on the nickel plating. In the present invention, the first layer wiring pattern including a portion to be a connection terminal is formed using a metal foil A such as a copper foil. However, by providing nickel plating as a base for gold plating, copper is a gold plating surface. It can be suppressed that the connection reliability with the bump is lowered.

  The thickness of the gold plating is desirably 0.01 to 3 μm. Thereby, the gold plating can ensure the bonding strength with the bumps, and can prevent oxidation of the underlying nickel plating. The thickness of the underlying nickel plating is preferably 1 to 20 μm. Furthermore, the thickness of the palladium plating provided on the nickel plating is preferably 0.01 to 1 μm. Thereby, since nickel plating suppresses the spreading | diffusion to the gold plating surface of copper, the reliability of bump connection is securable.

  In the present invention, the back electrode refers to an electrode provided on the surface (one surface) opposite to the surface (one surface) on which the connection terminal of the multilayer wiring board is provided, and is produced using the multilayer wiring board of the present invention. When a communication module or the like is mounted on another substrate, it is used to connect with a mounting terminal on the other substrate. The connection between the back electrode and the mounting terminal of another substrate can be performed by pressure bonding using a conductive adhesive or soldering.

  An embodiment of a method for manufacturing a multilayer wiring board according to the present invention will be described with reference to the drawings. First, as shown in FIG. 3, a core substrate 25 having a metal foil 38 on both sides and a metal foil A19 to be a first layer conductor 30 (shown in FIG. 4) on the surface layer are prepared (step (1)). On the metal foil 38 of the core substrate 25, the metal foil A19 that becomes the outermost first layer conductor 30 is directly laminated. As the metal foil A19, one having a size slightly smaller than the metal foil 38 of the core substrate 25 is used. Then, the 1st insulating layer 9 and metal foil B20 are laminated | stacked on one surface of metal foil A19 (process (2)). The first insulating layer 9 has a size that is slightly larger than the metal foil A19. In such a laminated state, the other surface of the metal foil A19 and the metal foil 38 of the core substrate 25 are in contact with each other and are not bonded to each other. The protruding first layer insulating layer 9 and the metal foil 38 of the core substrate 25 are in a bonded state. For this reason, since the other surface of the metal foil A19 is protected by the metal foil 38 of the core substrate 25, the other surface of the metal foil A19 is in a surface state even in the subsequent manufacturing process of the multilayer wiring board 1. Is maintained in its original state. In the embodiment of FIG. 3, the surface of the metal foil A19 is protected by the metal foil 38 of the core substrate 25. However, if the surface of the metal foil A19 can be protected and can be peeled off, the material / The method is not particularly limited, and a resin film or the like can also be used. In the embodiment of FIG. 3, the metal foil A19 is overlapped on the metal foils 38 on both surfaces of the core substrate 25 to perform the multilayering process. In this case, only one multilayering process is performed, and two sheets are formed. The multilayer wiring board 1 can be manufactured, and the production efficiency is good. In addition, since the multi-layer process is performed on both the upper and lower sides of the core substrate 25, warpage hardly occurs and trouble in the manufacturing process hardly occurs. Furthermore, since the core substrate 25 serves as a support, even in the case of the thin multilayer wiring substrate 1, handling in the manufacturing process is easy and workability is improved. It is also possible to perform the multilayering process by overlapping the metal foil A19 only on one metal foil 38 of the core substrate 25.

  Next, as shown in FIG. 4, a first interlayer connection hole 29 extending from the metal foil B20 to the first layer conductor 30 is formed in the first insulating layer 9 (step (3)). The first interlayer connection hole 29 is formed by forming an opening in the metal foil B20 by etching and irradiating the opening with a carbon dioxide gas laser or the like, or directly irradiating a UV laser or the like without forming an opening in the metal foil B20. The direct laser method can be used.

  Next, as shown in FIG. 4, filled via plating 21 a for electrically connecting the first layer conductor 30 and the metal foil B <b> 20 is performed in the first interlayer connection hole 29 and on the metal foil B <b> 20 (Step ( 4)). A first filled via 10 is formed in the first interlayer connection hole 29, and a plating layer 31 generated at the time of interlayer connection is formed on the metal foil B20. Further, the second layer conductor 33 is formed by both the metal foil B20 and the plating layer 31 generated at the time of interlayer connection. At this time, the surface roughness of the second layer conductor 33 is larger than that of the metal foil B20, although it depends on the thickness of the filled via plating 21a (plating layer 31 generated at the time of interlayer connection) formed on the surface of the metal foil B20. It will be in the state. The filled via plating 21a is formed so as to fill the first interlayer connection hole 29. The surface of the filled via plating 21a formed in the first interlayer connection hole 29 (the surface of the first filled via 10 portion) is: It is difficult to be completely flat with the surface of the filled via plating 21a formed on the metal foil B20. Therefore, although not shown, the surface of the filled via plating 21a formed in the first interlayer connection hole 29 (the surface of the first filled via 10 portion) is on the surface of the filled via plating 21a formed on the surface of the metal foil B20. On the other hand, protrusions and depressions are likely to occur.

  Next, as shown in FIG. 5, the second layer conductor 33 (shown in FIG. 4) after filled via plating is processed to form a second layer wiring pattern 11 (step (5)). In the second layer conductor 33 after filled via plating, the thickness of the metal foil B20 is added to the thickness of the plating layer 31 generated at the time of interlayer connection. is necessary. Further, as described above, the second layer conductor 33 after the filled via plating is likely to have a protrusion or a depression in the first filled via 10 portion. If it is necessary to reduce the thickness of the second layer conductor 33 or reduce the protrusion or depression of the first filled via 10 portion and make it flat to form a fine circuit, half-etching is required before circuit processing. Or buffing. When half etching, buffing, or the like is performed on the second layer conductor 33 after the filled via plating, the thickness of the second layer conductor 33 itself is reduced, and the protrusion or depression itself of the first filled via 10 portion is reduced. However, after these filled via plating 21a, half etching, buffing, and the like are performed, the surface roughness of the second layer conductor 33 is compared with the surface roughness of the metal foil B20 before these processes are performed. Enlarge significantly. In addition, since it is difficult to completely eliminate the protrusion and depression of the first filled via 10 portion, the flatness is inferior to the surface of the filled via plating 21a formed on the surface of the metal foil B20. On the other hand, the surface of the metal foil A19 disposed on the metal foil 38 of the core substrate 25 (the surface on the metal foil 38 side) is used to form the first filled via 10 and the second layer wiring pattern 11 on the metal foil B20 side. Even after processing such as filled via plating 21a, half etching, buffing, and the like, it is not exposed to these processing, so the initial state is maintained. For this reason, the metal foil A 19 maintains the surface roughness as the original copper foil and the flatness when laminated on the metal foil 38 of the core substrate 25. Further, the filled via plating 21a for interlayer connection is formed in the first interlayer connection hole 29 so as to be directly connected to the back surface (the first insulating layer 9 side) of the metal foil A19. Since it is not formed on the (metal foil 38 side), the conductor thickness does not increase. Therefore, when forming a fine circuit as the first layer wiring pattern 8 which is the outermost layer using the metal foil A19, if the thickness of the metal foil A19 is selected, the conductor thickness is reduced by half etching, buffing or the like. There is no need, and the metal foil A19 may be formed by etching or the like as it is, so that it is possible to form a wiring pattern having a high density and a flat surface with the same surface roughness as that of the metal foil.

  Next, steps (2) to (5) are repeated as many times as necessary on the second layer wiring pattern 11 (step (6)). Specifically, in this step (6), as shown in FIG. 5, the second insulating layer 12 and the metal foil C23 are laminated on the second layer wiring pattern 11 (step (2)), and then 6, the second interlayer connection hole 32 extending from the metal foil C23 to the second layer conductor 33 is formed in the second insulating layer 12 (step (3)), and in the second interlayer connection hole 32 and Filled via plating 21b for electrically connecting the second layer conductor 33 (shown in FIG. 4) and the metal foil C23 is performed on the metal foil C23 to form the second filled via 13 and the third layer conductor 35. Next, as shown in FIG. 7, after the third layer conductor 35 (shown in FIG. 6) after filled via plating is processed to form the third layer wiring pattern 14. (Step (5)), and further, the third insulating layer 15 and the metal foil D24 are formed on the third layer wiring pattern 14. Layer (step (2)), and a third interlayer connection hole 34 extending from the metal foil D24 to the third layer conductor 35 is formed in the third insulating layer 15 (step (3)). Then, filled via plating 21c for electrically connecting the third layer conductor 35 and the metal foil D24 is performed on the metal foil D24 to form the third filled via 16 and the fourth layer conductor 37 (step (4)). ). Next, the fourth layer conductor 37 after filled via plating is processed to form a fourth layer wiring pattern 17 (shown in FIG. 9) (step (5)). Note that the circuit processing of the fourth layer conductor 37 in this step (5) may be performed before the core substrate 25 and the multilayer wiring substrate 1 are separated, or these are separated as shown in FIG. It may be performed later or may be performed simultaneously with the circuit processing of the first layer conductor 30 described later.

  Next, as shown in FIG. 8, the core substrate 25 and the multilayer wiring substrate 1 are separated, and as shown in FIG. 9, the metal foil A <b> 19 that is the first layer conductor 30 is processed into a first layer wiring. By forming the pattern 8, the connection terminal 5 is formed immediately above the first interlayer connection hole 29 subjected to filled via plating (step (7)). On the metal foil A19, which is the first layer conductor 30, no plating layer is formed even during interlayer connection. Therefore, the thickness of the first layer conductor 30 is the thickness of the metal foil A19 itself. For this reason, circuit processing of the first layer conductor 30 can be performed only by etching the metal foil A19. Therefore, if the thickness of the metal foil A19 is set to 1 μm to 18 μm, a high-density wiring pattern can be formed. Is possible. For this reason, since it is not necessary to perform half etching or buffing on the first layer conductor 30, the surface smoothness is maintained. The circuit processing of the first layer conductor 30 in the step (7) may be performed simultaneously with the circuit processing of the fourth layer conductor 37 in the step (5). In this way, a smooth and accurate metal foil A19 is laminated on the metal foil 38 of the core substrate 25, and an insulating layer, a wiring pattern, and an insulating layer are interposed only on one surface of the metal foil A19. After forming the multilayer wiring board 1 by forming the interlayer connection for connecting the wiring patterns, the multilayer wiring board 1 and the core substrate 25 are separated to obtain a smooth and highly accurate metal foil A19. It is possible to form the first layer wiring pattern 8 which is the outermost layer. Accordingly, it is possible to provide a multilayer wiring board and a method for manufacturing the same that are high in density, excellent in flip chip connectivity and wire bond connectivity, and capable of ensuring a filter function when used as a wiring board constituting a SAW device. can do.

  Next, as shown in FIG. 9, the protective plating 22 is formed on the connection terminals 5 formed immediately above the first interlayer connection holes 29. As the protective plating 22, it is desirable to have nickel plating or nickel plating and gold plating. Thereby, the 1st layer wiring pattern 8 can be protected and flip chip connectivity and wire bond connectivity can be provided. Further, it is more desirable to form palladium plating between nickel plating and gold plating because the connection reliability with the electronic component element 3 is improved. Silver plating can also be used instead of gold plating.

  Hereinafter, examples of the present invention will be described with reference to FIGS. 3 to 9, but the present invention is not limited to these examples.

Example 1
First, as shown in FIG. 3, on both sides of a copper clad laminate 25 (MCL-E-67 manufactured by Hitachi Chemical Co., Ltd.) in which a 12 μm thick copper foil (metal foil 38) is laminated to a glass epoxy material, As the metal foil A19 having a narrower width than the copper foil (metal foil 38) of the copper clad laminate 25, the glossy surface of the copper foil having a thickness of 12 μm (3EC-VLP-12 manufactured by Mitsui Metal Mining Co., Ltd.) is a copper clad laminate. It arrange | positioned so as to oppose 25 copper foil (metal foil 38). The glossy surface (surface on the first layer side) of the copper foil prepared as the metal foil A19 had a maximum surface roughness (Rz) of less than 3 μm. A prepreg (GEA-679FG manufactured by Hitachi Chemical Co., Ltd.) is provided as the first insulating layer 9 on the outer side, and a carrier copper foil having a thickness of 18 μm is attached to an ultrathin copper foil having a thickness of 5 μm as the metal foil B20 on the outer side. The prepared ultrathin copper foil with carrier (MT18SDH5 manufactured by Mitsui Mining & Smelting Co., Ltd.) is constructed so that the roughened surface of the ultrathin copper foil of 5 μm adheres to the first insulating layer 9, and is laminated by a vacuum hot press. The laminated plate a26 was formed by peeling the carrier copper foil of 18 μm. The insulating layer thickness can be arbitrarily determined depending on the finished thickness requirement of the multilayer wiring board 1.

  Next, as shown in FIG. 4, a conformal mask having an opening with a diameter of 100 μm was formed on the copper foil (metal foil B20) on both outer sides of the laminate a26 by an etching method. The opening of the conformal mask is formed at a position where the interlayer connection with the metal foil A19 is made and the bump 4 for flip chip connection is disposed. HS201B (Hitachi Chemical Co., Ltd.), which is a palladium colloid catalyst, is provided on the copper foil (metal foil B20) and inside the non-through hole (first interlayer connection hole 29) by providing a non-through hole that becomes the first interlayer connection hole 29 by laser processing. After applying the catalyst core using a company-made product name), a base electroless plating layer having a thickness of 1 μm is formed using CUST2000 (manufactured by Hitachi Chemical Co., Ltd., product name). The first interlayer via hole 29) was filled with filled via plating 21a with electrolytic filled via plating solution to form the first filled via 10. The thickness of the plating layer 31 generated at the time of interlayer connection by the filled via plating 21a was 20 μm.

  Next, as shown in FIG. 5, a predetermined wiring pattern is formed by etching on both outer conductors (second layer conductor 33), and the surface of the resulting wiring pattern (second layer wiring pattern 11) is roughened. It roughens with the chemical treatment liquid Multibond MB-100 (manufactured by Nippon Macder Mid Co., Ltd., trade name). Next, a prepreg (GEA-679FG manufactured by Hitachi Chemical Co., Ltd.) was used as the second insulating layer 12, and a carrier copper foil having a thickness of 18 μm was applied to the outside as a metal foil C23 on a very thin copper foil having a thickness of 5 μm. An ultrathin copper foil with a carrier (MT18SDH5 manufactured by Mitsui Mining & Smelting Co., Ltd.) was constructed so that the roughened surface of the ultrathin copper foil of 5 μm was bonded to the second insulating layer 12 and laminated by vacuum hot pressing, 18 μm A laminate b27 was formed by removing the carrier copper foil. The insulating layer thickness can be arbitrarily determined depending on the finished thickness requirement of the multilayer wiring board 1.

  Next, as shown in FIG. 6, a non-through hole serving as the second interlayer connection hole 32 is provided in the laminate b27, and the interlayer 4 is connected to the third layer conductor 35 by the filled plating 21b and the bump 4 for flip chip connection. The second filled via 13 was formed at the position where the is disposed.

  By repeating the process of forming the wiring pattern, forming the laminated board, and forming the filled via, as shown in FIG. 7, each side of the copper clad laminated board 25 has a wiring pattern of four layers, and all filled vias A laminated plate c36 provided with the multilayer substrate 1 having a full stack structure formed directly above is formed. In the present embodiment, the multilayer wiring board 1 having a structure having four wiring patterns on one side is configured. However, by repeating the process of forming the wiring pattern, forming the laminate, and forming the filled via, A laminated board having a structure having a wiring pattern having an arbitrary number of layers as described above can be formed.

  As shown in FIG. 8, the copper clad laminate 25 and each of the upper and lower multilayer wiring boards 1 are respectively cut by an end portion of the narrow metal foil A19 or by a cutting portion 28 provided inside thereof. Separated, two multilayer wiring boards 1 were obtained. At this time, the surface roughness of the metal foil A19 was less than 3 μm in terms of the maximum roughness (Rz), and the metal foil A19 was protected by the copper clad laminate 25 with the original surface roughness. In the present embodiment, the fourth layer conductor 37 is formed and then cut by the cutting portion 28. However, after forming the second layer conductor 33 and after forming the third layer conductor 35, the end portion of the narrow metal foil A19 or By cutting with the cutting part 28 provided on the inner side, a laminated plate having a two-layer structure and a three-layer structure can be formed. At this time, the surface roughness of the metal foil A19 is 3 μm at the maximum roughness (Rz). The metal foil A19 was protected by the copper clad laminate 25 with the original surface roughness.

  Next, as shown in FIG. 9, the first layer wiring pattern is formed by circuit processing the outermost layers (the metal foil A19 and the fourth layer conductor 37 which are the first layer conductors 30) of the separated multilayer wiring substrate 1 by an etching method. 8 and the fourth layer wiring pattern 17 were formed. At this time, a part of the first layer wiring pattern 8 was formed as a part to be the flip chip connection terminal 5, and the part to be the flip chip connection terminal 5 was arranged immediately above the first filled via 10. That is, filled vias are formed in a full stack structure, and on the uppermost layer immediately above these filled vias, a portion to be a flip chip connection terminal 5 formed by processing the metal foil A19 is disposed. At this time, the surface roughness of the metal foil A19 was less than 3 μm in terms of the maximum roughness (Rz), and the metal foil A19 was protected with the original surface roughness.

  Next, as shown in FIG. 9, a solder resist 18 was formed in a predetermined region excluding a portion to be the flip chip connection terminal 5 and a portion to be the back electrode 7. Thereafter, as protective plating 22, electroless nickel plating with a thickness of 0.03 μm is performed on electroless nickel plating with a thickness of 10 μm, electroless gold plating with a thickness of 0.05 μm is performed on the palladium plating, and flip chip The connection terminal 5 and the back electrode 7 were formed to complete the multilayer wiring board 1. The surface roughness of the protective plating 22 on the upper side of the connection terminal 5 and the protective plating 22 on the first layer wiring pattern is 0.5 μm to 2.9 μm in maximum roughness (Rz), and the original surface of the metal foil A19 It was equivalent to roughness.

(Example 2)
The surface of the copper foil prepared as the metal foil A19 (surface on the first layer side) is a multilayer wiring board in the same manner as in Example 1 except that the maximum surface roughness (Rz) is less than 5 μm. 1 was produced. As for the surface roughness of the protective plating 22 on the upper part of the connection terminal 5 and the protective plating 22 on the first layer wiring pattern, the maximum roughness (Rz) was 0.7 μm to 4.8 μm.

(Example 3)
The surface of the copper foil prepared as the metal foil A19 (the surface on the first layer side) is a multilayer wiring board in the same manner as in Example 1 except that the maximum surface roughness (Rz) is less than 8 μm. 1 was produced. As for the surface roughness of the protective plating 22 on the upper side of the connection terminal 5 and the protective plating 22 on the first layer wiring pattern, the maximum roughness (Rz) was 0.9 μm to 7.7 μm.

Example 4
The flip chip connection terminal 5 is formed immediately above the first filled via 10, but when the first filled via 10, the second filled via 13, and the third filled via 16 are shifted from each other and viewed from the surface layer side, any filled via is formed. Also formed so as not to overlap. Other than this, the multilayer wiring board 1 was fabricated in the same manner as in Example 1. The surface roughness of the protective plating 22 on the upper side of the connection terminal 5 and the protective plating 22 on the first layer wiring pattern is 0.5 μm to 2.9 μm in maximum roughness (Rz), and the original surface of the metal foil A19 It was equivalent to roughness.

(Reference Example 1)
As the metal foil A19, a copper foil having a thickness of 12 μm (3EC-VLP-12 manufactured by Mitsui Mining & Smelting Co., Ltd.) was prepared, and the polishing paper was applied to the surface (surface on the first layer side) of the metal foil A19. Polishing was used to prepare a material having a maximum surface roughness (Rz) of 8 μm or more. Other than this, the multilayer wiring board 1 was fabricated in the same manner as in Example 1. As for the surface roughness of the protective plating 22 on the upper part of the connection terminal 5 and the protective plating 22 on the first layer wiring pattern, the maximum roughness (Rz) exceeded 8 μm.

(Comparative Example 1)
The wiring pattern on the electronic component element 3 mounting surface is not formed by the first layer wiring pattern 8 formed by the metal foil A19, but the fourth layer conductor having the metal foil D24 and the plating layer 31 generated at the time of interlayer connection. 37 was formed by a fourth layer wiring pattern 17 formed by circuit processing. Then, the protective plating 22 was performed on the 4th layer wiring pattern 17 including the part used as the connection terminal 5, and the connection terminal 5 was formed. Hereafter, a process is shown.

  In the same manner as in Example 1, by repeating the process of forming the wiring pattern, forming the laminated board, and forming the filled via, the four-layer wiring on one side is formed on both sides of the copper-clad laminated board 25 as shown in FIG. The laminated board c36 provided with the multilayer distribution board 1 which has a pattern was formed.

  Next, the fourth layer conductor 37 was half-etched. The purpose of this half-etching is that in Comparative Example 1, it is necessary to form a portion that becomes a fine connection terminal 5 by the fourth-layer conductor 37 that is thicker than the metal foil A19. This is because it is easy to perform fine circuit processing. The thickness of the fourth layer conductor 37 is the sum of the thickness (5 μm) of the metal foil D24 and the thickness (20 μm) of the plating layer 31 generated at the time of interlayer connection by the filled via plating 21c, and is approximately 25 μm. The half etching amount was 13 μm in order to make the thickness of the fourth layer conductor 37 equivalent to that of the metal foil A19, and the remaining thickness of the fourth layer conductor 37 was 12 μm equivalent to that of the metal foil A19.

  Next, as shown in FIG. 8, the copper clad laminate 25 and one multilayer wiring board above and below the copper clad laminate 25 are cut by an end portion of a narrow metal foil A19 or by a cutting portion 28 provided inside thereof. 1 was separated to obtain two multilayer wiring boards 1.

  Next, as shown in FIG. 9, the first layer wiring pattern is formed by circuit processing the outermost layers (the metal foil A19 and the fourth layer conductor 37 which are the first layer conductors 30) of the separated multilayer wiring substrate 1 by an etching method. 8 and the fourth layer wiring pattern 17 were formed. A solder resist 18 was formed at a predetermined position excluding a part to be the flip chip connection terminal 5 and a part to be the back surface electrode 7 (Comparative Example 1 in FIG. 9 differs from the flip chip connection terminal 5 and the back surface electrode 7 in FIG. 9). The position of is upside down.) Thereafter, as protective plating 22, electroless nickel plating having a thickness of 0.03 μm is applied on electroless nickel plating having a thickness of 10 μm, and electroless gold plating having a thickness of 0.05 μm is applied on the palladium plating. 1 was completed. As for the surface roughness of the protective plating 22 on the upper part of the connection terminal 5 and the protective plating 22 on the first layer wiring pattern, the maximum roughness (Rz) exceeded 8 μm.

(Reference Example 2)
In the multilayer wiring board 1 of FIG. 9, the connection terminal 5 is provided not on the first filled via 10 but on the shifted first insulating layer 9, and the first filled via 10, the second filled via 13, and the third filled via 16 are provided. These positions were shifted to each other, and when viewed from the surface layer side, each filled via was formed so as not to overlap. Except this, it is the same as the first embodiment.

  Table 1 shows the results of Examples 1 to 4, Reference Example 1, Comparative Example 1, and Reference Example 2. In Examples 1 to 3, since the filled via has a full stack structure, and the surface roughness (Rz) of the protective plating 22 of the first layer wiring pattern 8 is less than 8 μm, the flip chip connectivity and the wire bond connectivity are good. Met. In Example 4, although a full stack structure is not used, since the connection terminal is disposed immediately above the first filled via, transmission of ultrasonic waves and heat is ensured, and flip chip connectivity and wire bond connectivity are good. It was. On the other hand, in Reference Example 1 and Comparative Example 1, filled vias are provided in a full stack structure, but since the surface roughness (Rz) of the protective plating of the first layer wiring pattern exceeds 8 μm, flip chip connectivity, The wire bond connectivity was not good. In Reference Example 2, the surface roughness (Rz) of the protective plating of the first layer wiring pattern is as small as 0.5 to 2.9 μm, but the filled vias are not arranged in a full stack structure, so flip chip connectivity, wire Bond connectivity was not good.

  The surface roughness is the maximum roughness Rz defined in JIS B 0601 (2001), and was measured using a stylus type surface roughness meter Surf Test SV-3000 (trade name, manufactured by Mitutoyo Corporation).

  The following evaluation was performed in order to evaluate flip chip connectivity. The flip chip connection was performed by aligning the connection terminals of the multilayer wiring board and the gold bumps of the electronic component element so as to face each other, and then performing flip chip connection from above with a flip chip bonder. The crimping conditions for flip chip connection were held for 4 seconds while raising the temperature to 230 ° C. and applying 50 g per bump while using ultrasonic waves. Removed from flip chip bonder and checked flip chip connection. The case where there is no unconnected bump in the entire electronic component element is indicated by “◯”, and the case where there is an unconnected bump is indicated by “X”.

  The following evaluation was performed in order to evaluate wire bond connectivity. Using a gold wire with a diameter of 0.025 mm, the temperature is 140 ° C., the first bonding side has an ultrasonic application time of 40 milliseconds, the load is 75 grams, and the 2nd bonding side has an ultrasonic application time of 45 milliseconds and the load is 100 grams. Under the conditions, the ultrasonic thermocompression bonding method was used, and the pull strength by the bond tester was set as “◯” when 7 g or more, “Δ” when 5 g or more but less than 7 g, and “x” when less than 5 g.

DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board, 2 ... Communication module, 3 ... Electronic component element or SAW piezoelectric element, 4 ... (For flip chip connection) Bump, 5 ... (Flip chip) connection terminal, 6 ... Resin for molding, 7 ... Back surface Electrode, 8 ... First layer wiring pattern, 9 ... First insulating layer, 10 ... First filled via, 11 ... Second layer wiring pattern, 12 ... Second insulating layer, 13 ... Second filled via, 14 ... Third layer wiring Pattern: 15 ... 3rd insulating layer, 16 ... 3rd filled via, 17 ... 4th layer wiring pattern, 18 ... Solder resist, 19 ... Metal foil A, 20 ... Metal foil B, 21a, 21b, 21c ... Filled via plating, 22 ... protective plating, 23 ... metal foil C, 24 ... metal foil D, 25 ... copper-clad laminate or core substrate, 26 ... laminate a, 27 ... laminate b, 28 ... cutting 29: 1st interlayer connection hole, 30 ... 1st layer conductor, 31 ... Plating layer produced at the time of interlayer connection, 32 ... 2nd interlayer connection hole, 33 ... 2nd layer conductor, 34 ... 3rd interlayer connection hole 35 ... Third layer conductor, 36 ... Laminated plate c, 37 ... Fourth layer conductor, 38 ... Metal foil (of core substrate), 39 ... Active surface of SAW piezoelectric element

Claims (12)

A multilayer wiring board having an interlayer connection in which wiring patterns and insulating layers are alternately provided and which connects between wiring patterns through the insulating layers,
The interlayer connection is formed by filled vias by plating,
The outermost first layer wiring pattern is formed by the metal foil A disposed on the interlayer connection and connected to the back surface of the filled via by the plating ,
On the inner layer side of the first layer wiring pattern of the outermost layer, the metal foil B and the plating forming the second layer wiring pattern are arranged in this order via the first insulating layer,
Furthermore, on the inner layer side of the second layer wiring pattern, the metal foil C and the plating forming the third layer wiring pattern are arranged in this order via the second insulating layer,
It said first insulating layer and the second insulating layer, a high Tg (glass transition temperature) material or a low alpha (thermal expansion coefficient) Zaidea Ru multilayer wiring board.   The wiring of the outermost layer according to claim 1, wherein after forming an insulating layer, a wiring pattern, and an interlayer connection for connecting each wiring pattern only on one surface of the metal foil, circuit processing is performed on the metal foil. A multilayer wiring board in which a pattern is formed of a metal foil.   3. The multilayer wiring board according to claim 1, wherein the interlayer connection formed by filled vias is provided in a substantially column shape over the entire thickness direction of the multilayer wiring board.   4. The multilayer wiring board according to claim 1, wherein the outermost wiring pattern has nickel plating, nickel plating and gold plating, nickel plating, palladium plating and gold plating as protective plating.   5. The multilayer wiring board according to claim 1, wherein the metal foil constituting the outermost wiring pattern is a copper foil having a thickness of 1 to 18 [mu] m.   6. The multilayer wiring board according to claim 1, wherein the maximum roughness (Rz) of the surface of the protective plating formed on the outermost wiring pattern is less than 8 μm.   7. The multilayer wiring board according to claim 1, wherein the outermost wiring pattern located immediately above the interlayer connection forms a flip chip connection terminal or a wire bond connection terminal.   An electronic device in which an electronic component element is mounted using a flip chip connection terminal or a wire bond connection terminal formed by the wiring pattern of the outermost layer of the multilayer wiring board according to claim 7.   9. The electronic device according to claim 8, wherein a SAW piezoelectric element or PA element is mounted as the electronic component element to form a communication module. A method for manufacturing a multilayer wiring board for manufacturing the multilayer wiring board according to claim 1,
A step (1) of preparing a metal foil A to be an outermost first layer conductor;
A step (2) of laminating a first insulating layer and a metal foil B serving as a second layer conductor on the metal foil A;
Forming an interlayer connection hole from the second layer conductor to the first layer conductor in the first insulating layer (3);
(4) performing filled via plating for electrically connecting the first layer conductor and the second layer conductor in the interlayer connection hole and on the second layer conductor;
A step (5) of forming a second layer wiring pattern by processing a circuit of the second layer conductor after the filled via plating;
A step (6) of repeating the steps (2) to (5) as many times as necessary on the second layer wiring pattern;
Forming a connection terminal directly above the interlayer connection hole subjected to the filled via plating by forming a first layer wiring pattern by processing the metal foil A as the first layer conductor;
A method of manufacturing a multilayer wiring board having   11. After the step of forming a connection terminal immediately above an interlayer connection hole subjected to filled via plating by forming a first layer wiring pattern by processing a metal foil A as a first layer conductor in claim 10 A method for manufacturing a multilayer wiring board, wherein protective plating is formed on the connection terminals. In claim 10 or 11,
A core substrate having metal foils on both sides is prepared, and the metal foil A that is the first layer of the surface layer prepared in the step (1) is directly stacked on the metal foil of the core substrate, and then the steps (2) to (2) to (6)
Then, the step (9) of separating the plurality of wiring layers and the core substrate at the interface between the metal foil and the metal foil A of the core substrate;
Forming a connection terminal directly above the interlayer connection hole subjected to filled via plating by processing the metal foil A as the first layer conductor to form a first layer wiring pattern;
A method of manufacturing a multilayer wiring board having

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