JP5679735B2 - パッケージ基板のハンドリング方法 - Google Patents
パッケージ基板のハンドリング方法 Download PDFInfo
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- JP5679735B2 JP5679735B2 JP2010182712A JP2010182712A JP5679735B2 JP 5679735 B2 JP5679735 B2 JP 5679735B2 JP 2010182712 A JP2010182712 A JP 2010182712A JP 2010182712 A JP2010182712 A JP 2010182712A JP 5679735 B2 JP5679735 B2 JP 5679735B2
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- chip
- package substrate
- chips
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- 238000000034 method Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 39
- 239000000853 adhesive Substances 0.000 claims description 24
- 230000001070 adhesive effect Effects 0.000 claims description 24
- 238000003860 storage Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 14
- 238000005520 cutting process Methods 0.000 claims description 10
- 239000004820 Pressure-sensitive adhesive Substances 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 description 14
- 230000004308 accommodation Effects 0.000 description 5
- 238000003825 pressing Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Supply And Installment Of Electrical Components (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Packaging Frangible Articles (AREA)
Description
4 フレーム基板
6 チップ
8 バンプ
10 分割予定ライン
12 収容トレイ
14 チップ収容部
16 側壁
18 粘着材
18a 接着面
20 固定治具
22 吸引テーブル
Claims (1)
- 複数の分割予定ラインが形成されたパッケージ基板をハンドリングするパッケージ基板のハンドリング方法であって、
パッケージ基板の各チップに対応した位置に吸引穴を有する固定治具を介して切削装置の吸引テーブルでパッケージ基板を保持する保持ステップと、
該保持ステップを実施した後、該分割予定ラインに沿って該パッケージ基板を分割して複数のチップを形成する分割ステップと、
該分割ステップを実施した後、該パッケージ基板を収容可能な大きさの凹部からなるチップ収容部と、該チップ収容部を囲繞する側壁と、該チップ収容部内に配設された複数のチップが接着される接着面を有する粘着材と、を備えた収容トレイの該粘着材の接着面を、該分割ステップで分割された複数のチップに押圧して複数のチップをまとめて該粘着材の接着面に接着する一括接着ステップと、
該一括接着ステップを実施した後、複数のチップが該チップ収容部内に接着された該収容トレイを搬送する搬送ステップと、
を備えたことを特徴とするパッケージ基板のハンドリング方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010182712A JP5679735B2 (ja) | 2010-08-18 | 2010-08-18 | パッケージ基板のハンドリング方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010182712A JP5679735B2 (ja) | 2010-08-18 | 2010-08-18 | パッケージ基板のハンドリング方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012043914A JP2012043914A (ja) | 2012-03-01 |
JP5679735B2 true JP5679735B2 (ja) | 2015-03-04 |
Family
ID=45899901
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2010182712A Active JP5679735B2 (ja) | 2010-08-18 | 2010-08-18 | パッケージ基板のハンドリング方法 |
Country Status (1)
Country | Link |
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JP (1) | JP5679735B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6037372B2 (ja) * | 2011-08-03 | 2016-12-07 | 株式会社ディスコ | パッケージ基板分割装置 |
KR102043378B1 (ko) * | 2012-10-22 | 2019-11-12 | 삼성전자주식회사 | 캐비티를 갖는 웨이퍼 캐리어 |
JP6605946B2 (ja) * | 2015-12-24 | 2019-11-13 | 株式会社ディスコ | チップ収容トレイからチップをピックアップする方法 |
JP7285669B2 (ja) * | 2019-03-22 | 2023-06-02 | 株式会社ディスコ | 加工装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04267356A (ja) * | 1991-02-22 | 1992-09-22 | Nec Corp | 半導体素子搬送容器 |
JP4388640B2 (ja) * | 1999-09-10 | 2009-12-24 | 株式会社ディスコ | Csp基板保持部材及び該csp基板保持部材が載置されるcsp基板用テーブル |
JP4546626B2 (ja) * | 2000-08-29 | 2010-09-15 | 株式会社ディスコ | 半導体素子のピックアップ方法 |
JP4078825B2 (ja) * | 2001-10-30 | 2008-04-23 | ソニー株式会社 | 回路基板の製造方法、並びに表示装置の製造方法 |
JP4555032B2 (ja) * | 2004-09-03 | 2010-09-29 | シーエステック株式会社 | トレイ |
JP4694247B2 (ja) * | 2005-04-18 | 2011-06-08 | 株式会社リコー | 半導体集積回路装置用収納トレイ |
JP2007184465A (ja) * | 2006-01-10 | 2007-07-19 | Renesas Technology Corp | 半導体チップトレイ |
JP4846411B2 (ja) * | 2006-03-30 | 2011-12-28 | 株式会社ディスコ | 半導体パッケージ用治具 |
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2010
- 2010-08-18 JP JP2010182712A patent/JP5679735B2/ja active Active
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Publication number | Publication date |
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JP2012043914A (ja) | 2012-03-01 |
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