JP5629926B2 - 半導体パッケージおよびその製造方法 - Google Patents

半導体パッケージおよびその製造方法 Download PDF

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Publication number
JP5629926B2
JP5629926B2 JP2010179978A JP2010179978A JP5629926B2 JP 5629926 B2 JP5629926 B2 JP 5629926B2 JP 2010179978 A JP2010179978 A JP 2010179978A JP 2010179978 A JP2010179978 A JP 2010179978A JP 5629926 B2 JP5629926 B2 JP 5629926B2
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Prior art keywords
lid
semiconductor package
cavity
peripheral wall
metallized layer
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JP2010179978A
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English (en)
Japanese (ja)
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JP2012039022A5 (https=
JP2012039022A (ja
Inventor
白石　晶紀
晶紀 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2010179978A priority Critical patent/JP5629926B2/ja
Publication of JP2012039022A publication Critical patent/JP2012039022A/ja
Publication of JP2012039022A5 publication Critical patent/JP2012039022A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Pressure Welding/Diffusion-Bonding (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
JP2010179978A 2010-08-11 2010-08-11 半導体パッケージおよびその製造方法 Active JP5629926B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010179978A JP5629926B2 (ja) 2010-08-11 2010-08-11 半導体パッケージおよびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010179978A JP5629926B2 (ja) 2010-08-11 2010-08-11 半導体パッケージおよびその製造方法

Publications (3)

Publication Number Publication Date
JP2012039022A JP2012039022A (ja) 2012-02-23
JP2012039022A5 JP2012039022A5 (https=) 2013-08-08
JP5629926B2 true JP5629926B2 (ja) 2014-11-26

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ID=45850656

Family Applications (1)

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JP2010179978A Active JP5629926B2 (ja) 2010-08-11 2010-08-11 半導体パッケージおよびその製造方法

Country Status (1)

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JP (1) JP5629926B2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5979994B2 (ja) * 2012-06-12 2016-08-31 新光電気工業株式会社 電子装置
JP6155617B2 (ja) * 2012-12-13 2017-07-05 セイコーエプソン株式会社 電子デバイス、電子機器および移動体
CN114361122B (zh) * 2021-08-11 2025-03-11 华为技术有限公司 功率模块的封装结构及封装方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010178113A (ja) * 2009-01-30 2010-08-12 Kyocera Kinseki Corp 圧電デバイス

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Publication number Publication date
JP2012039022A (ja) 2012-02-23

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