JP5627789B2 - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
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- JP5627789B2 JP5627789B2 JP2013526793A JP2013526793A JP5627789B2 JP 5627789 B2 JP5627789 B2 JP 5627789B2 JP 2013526793 A JP2013526793 A JP 2013526793A JP 2013526793 A JP2013526793 A JP 2013526793A JP 5627789 B2 JP5627789 B2 JP 5627789B2
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- electrode
- semiconductor element
- bonding
- copper
- power semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims description 186
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000010949 copper Substances 0.000 claims description 171
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 167
- 229910052802 copper Inorganic materials 0.000 claims description 167
- 238000007747 plating Methods 0.000 claims description 111
- 239000000758 substrate Substances 0.000 claims description 72
- 229910052709 silver Inorganic materials 0.000 claims description 53
- 239000004332 silver Substances 0.000 claims description 53
- 239000000463 material Substances 0.000 claims description 48
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 24
- 239000002245 particle Substances 0.000 claims description 19
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 10
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 229910010293 ceramic material Inorganic materials 0.000 claims description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- 238000012360 testing method Methods 0.000 description 25
- 230000000052 comparative effect Effects 0.000 description 24
- 238000005304 joining Methods 0.000 description 21
- 239000010408 film Substances 0.000 description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 230000005856 abnormality Effects 0.000 description 9
- 238000005219 brazing Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 230000035939 shock Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 6
- 238000011156 evaluation Methods 0.000 description 6
- 239000010419 fine particle Substances 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 239000005416 organic matter Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- FOIXSVOLVBLSDH-UHFFFAOYSA-N Silver ion Chemical compound [Ag+] FOIXSVOLVBLSDH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910000365 copper sulfate Inorganic materials 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- DOBRDRYODQBAMW-UHFFFAOYSA-N copper(i) cyanide Chemical compound [Cu+].N#[C-] DOBRDRYODQBAMW-UHFFFAOYSA-N 0.000 description 2
- PEVJCYPAFCUXEZ-UHFFFAOYSA-J dicopper;phosphonato phosphate Chemical compound [Cu+2].[Cu+2].[O-]P([O-])(=O)OP([O-])([O-])=O PEVJCYPAFCUXEZ-UHFFFAOYSA-J 0.000 description 2
- 238000002848 electrochemical method Methods 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000002082 metal nanoparticle Substances 0.000 description 2
- 239000004848 polyfunctional curative Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 150000003585 thioureas Chemical class 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 101000663444 Homo sapiens Transcription elongation factor SPT4 Proteins 0.000 description 1
- 102100022068 Serine palmitoyltransferase 1 Human genes 0.000 description 1
- 101710122478 Serine palmitoyltransferase 1 Proteins 0.000 description 1
- 102100038997 Transcription elongation factor SPT4 Human genes 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 150000007530 organic bases Chemical class 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
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- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Description
本発明の実施の形態1にかかる電力用半導体装置、および電力用半導体装置に用いる回路基板について、図に基づいて説明する。図1〜図5は、本発明の実施の形態1にかかる電力用半導体装置と回路基板について説明するためのもので、図1は電力用半導体装置の部分断面図、図2は回路基板の製造方法を説明するためのもので、図2(a)〜図2(c)は、各工程における断面図である。図3は電力用半導体装置の製造方法のうちの、回路基板に電力用半導体素子を接合する方法を説明するためのもので、図3(a)〜図3(c)は、各行程中の状態を示し、図3(a)は上面を、図3(b)と図3(c)は断面を示す。そして、図4は本実施の形態にかかる電力用半導体装置の接合信頼性を説明するためのもので、図4(a1)と図4(a2)は実施例として作成した回路基板と半導体素子との接合体の寿命試験前後の断面図、図4(b1)と図4(b2)は比較例として作成した回路基板と半導体素子との接合体の寿命試験前後の断面図である。また、図5は本実施の形態にかかる電力用半導体装置の接合信頼性を説明するためのもので、銅電極の表面硬度と密着強度との関係を示すグラフである。
電力用半導体素子も制御用半導体素子も原理的には同じ半導体素子である。しかし、電力用半導体素子の場合、主電流、つまり、大電流を流すために、必要とされる回路基板の仕様(電極の導電性や放熱性)が異なる。そのために、背景技術で説明したような課題が生じる。そこで、本発明の各実施の形態では、半導体素子には、主電力を制御する電力用半導体素子を用いることとする。
電極付絶縁基板である回路基板2は絶縁基板(窒化珪素)21の両面に、スパッタ膜(Cu)22a、22b(まとめて金属薄膜22)、厚さ500μmのめっき電極(Cu)23a、23b(まとめて銅めっき電極23)をそれぞれ順に積層するように形成したものである。この銅めっき電極23は、それぞれ厚みが150μm〜500μmの範囲を好適範囲として、本実施の形態では500μmに設定し、少なくとも電力用半導体素子1との接合面PB側の銅めっき電極23aについては、ビッカース硬さが70HV以上になるようにしている。また、回路基板2には、窒化珪素に限らず、アルミナ、窒化アルミニウムなどを絶縁基板21として用いることができる。発熱量の大きな電力用半導体装置全体の放熱の観点から、熱伝導率20W/m・K以上の材料を用いることが望ましく、熱伝導率70W/m・K上の材料がさらに望ましい。
電力用半導体素子1と回路基板2とは焼結銀接合層4によって接合される。焼結銀接合層4は、銀微粒子を有機基剤中に懸濁させてペースト状にした焼結性銀粒子接合材(銀ナノペースト)を加熱することにより、有機物で覆われていた銀微粒子表面が互いに接触することで、銀の融点よりも低い温度で焼結することにより形成される。
銀ナノペーストで電力用半導体素子1を回路基板2の一方の面(図では23a側)に接合した後、他方の面(同じく、23b側)のめっき電極(Cu)23bには、はんだ等の接合材5を用いてベース板(Cu等)3を接合する。さらに、電力用半導体素子1の回路基板2に対向する面に対して反対側の面(能動面)に形成された金属膜15(素子電極)には、はんだ等の接合材7を用いてリード板6が接合され、電気配線上は電力用半導体装置が完成する。その後、一般的に用いられる封止技術により樹脂等でパッケージングされる。
図3(a)に示すように、銅めっき電極23aの表面に、6mm角の開口OM4で、厚さ0.2mmのステンレスマスクM4を用いて、開口部分OM4に焼結性銀粒子接合材である銀ナノペースト4Pを印刷する。そして、図3(b)に示すように、印刷した銀ナノペースト4Pの表面に、位置を合わせて電力用半導体素子1を載置して、仮接合体となす。つぎに、仮接合体に100℃、10min間のプリヒート処理を行った後、5MPaの加圧をしながら、350℃まで昇温する。350℃に到達してから、5分間保持することにより、銀ナノペーストが含有する銀ナノ粒子(微粒子)の表面を覆っていた有機物が分解され、露出した微粒子同士が焼結し、図3(c)に示すように銀の焼結接合層4が形成される。その後、空冷させることにより、回路基板2と電力用半導体素子1との接合体を得た。その後、上述したようにベース板3やリード板6をさらに接合することにより、電力用半導体装置を得ることができる。銀ナノペースト4Pとしては、例えば、DOWA社製造T2W−A2を用いることができる。上記加熱接合は、接合装置(アスリートFA:加熱圧着ユニット)を用いて行った。
比較例のサンプル(接合体)は、以下の方法で作成した。
半導体素子は、本実施の形態1で使用した電力用半導体素子1と同じ方法で作製した。回路基板としては、図4(b1)に示すように、20mm角、厚さ1.0mmの窒化珪素からなる絶縁基板21の両面(図3と同様に電力用半導体素子との接合面PBと反対側の部分は記載を省略)に、18mm角、厚さ500μmの銅板25を、ろう材24で接合したものを使用した。接合方法(接合体の製造方法)は、本実施の形態1と同様である。実施例サンプルとして3個(SE1−1〜SE1−3)、および比較例サンプルとして3個(SC1−1〜SC1−3)ずつ作製した。
このように構成された接合体のサンプルを、ヒートショック試験機(エスペック社:冷熱衝撃試験機TSA−101S−W)に投入し、処理条件は−40℃〜200℃(1サイクル−40℃:30分保持/200℃:30分保持)で行った。200サイクルごとにシェア測定器(Dage社:シェア測定器HS4000)による密着強度測定を行った。密着強度判定は、30kgf/チップ以上かけてもはがれない場合を密着性異常なしとし、30kgf/チップ未満ではがれた場合を強度低下有りとした。なお、ビッカース硬さ試験器(ミツトヨ:MVK−H2)を用い、実施例の銅めっき電極23aと、比較例の銅板電極25aの表面の硬度を測定荷重100g、測定時間10秒の条件で測定した。接合前における実施例サンプルの銅めっき電極23aの硬度は70HV、比較例サンプルの銅板電極25aの硬度は30HVであった。
めっき電極は、密着強度比較試験における実施例サンプル(SE1−1〜1−3)と同様に、約600μm厚にまでめっき後、機械研磨により500μmの厚さに削って形成した。研磨直後の硬度は120HV以上であったが、予め窒素雰囲気下で熱処理することで20〜120HVの範囲内で調整した。そして、硬度を調整した電極に対して、密着強度比較試験と同様に電力用半導体素子を接合し、−40℃〜200℃の冷熱衝撃試験を行い、400サイクルを経過後に密着強度を測定した。
上記実施の形態1においては、電力用半導体素子と接合する電極の全厚みをめっきで形成する例について説明した。本実施の形態2においては、硬度を保持する必要のある厚みを特定し、硬度の必要な電力用半導体素子との接合面PBから所定深さの厚み分をめっきで形成し、絶縁基板側の部分は、硬度を限定しない銅板(ろう付け)で形成するようにした。他の構成については、実施の形態1と同様である。
電極付絶縁基板である回路基板202は絶縁基板(窒化珪素)21の両面に、それぞれ下地として厚さ500μmの銅板26Ba、26Bb(まとめて下地銅板26B)をろう材24a、24b(まとめてろう材24)で接合し、さらに、下地銅板26Bの上に、厚さ50μm以上の銅めっき層26Pa、26Pb(まとめて銅めっき層26P)を形成したものである。つまり、回路基板202の両面にそれぞれ形成された銅電極26a、26b(まとめて銅電極26)は、硬度を特定しない下地銅板26B上に所定以上の硬度(70HV)を有する銅めっき層26Pが所定厚さ以上形成されているものである。
図3(a)に示すように、銅電極26aの表面に、6mm角の開口OM4で、厚さ0.2mmのステンレスマスクM4を用いて、開口部分OM4に銀ナノペースト4Pを印刷する。そして、図3(b)に示すように、印刷した銀ナノペースト4Pの表面に、位置を合わせて電力用半導体素子1を載置して、仮接合体となす。つぎに、仮接合体に100℃、10min間のプリヒート処理を行った後、5MPaの加圧をしながら、350℃まで昇温する。350℃に到達してから、5分間保持することにより、銀ナノペーストが含有する銀ナノ粒子(微粒子)の表面を覆っていた有機物が分解され、露出した微粒子同士が焼結し、図3(b)に示すように銀の焼結接合層4が形成される。その後、空冷させることにより、回路基板202に電力用半導体素子1との接合体を得た。その後、上述したようにベース板3やリード板6をさらに接合することにより、図6に示すような電力用半導体装置を得ることができる。銀ナノペースト4Pとしては、例えば、DOWA社製造T2W−A2を用いることができる。上記加熱接合は、接合装置(アスリートFA:加熱圧着ユニット)を用いて行った。
比較例のサンプル(接合体)は、実施の形態1における比較例と同様に、回路基板としては、20mm角、厚さ1.0mmの窒化珪素からなる絶縁基板21の両面に、18mm角、厚さ500μmの銅板25を、ろう材24で接合したものを使用した。接合方法(接合体の製造方法)は、本実施の形態1および2と同様である。実施例サンプルとして3個(SE2−1〜SE2−3)、および比較例サンプルとして3個(SC2−1〜SC2−3)ずつ作製した。
このように構成された接合体のサンプルを、実施の形態1における密着強度比較試験と同様に、ヒートショック試験機(エスペック社:冷熱衝撃試験機TSA−101S−W)に投入し、−40℃〜200℃(1サイクル−40℃:30分保持/200℃:30分保持)の処理条件で行った。200サイクルごとにシェア測定器(Dage社:シェア測定器HS4000)による密着強度測定を行った。密着強度判定も、同様に、30kgf/チップ以上かけてもはがれない場合を密着性異常なしとし、30kgf/チップ未満ではがれた場合を強度低下有りとした。なお、ビッカース硬さ試験器(ミツトヨ:MVK−H2)を用い、実施例の銅電極26aと、比較例の銅板電極25aの表面の硬度を測定荷重100g、測定時間10秒の条件で測定した。接合前における実施例サンプルの銅めっき電極23aの硬度は70HV、比較例サンプルの銅板電極25aの硬度は30HVであった。
なお、上記実施の形態2の銅電極26aでは、絶縁基板21の側の銅板26Baの硬度はろう付けにより焼鈍されているため、電力用半導体素子1の側の銅めっき層26Paの硬度よりも小さくなる。このように銅電極26aはその硬度が絶縁基板21の側で小さくなるように深さ方向に硬度の分布を有するようにしてもよい。例えば、厚み方向の全範囲にわたって硬度を一律にして、絶縁基板21の側の硬度が大きくなると、冷熱衝撃が加わった場合に絶縁基板21のセラミック部分にクラックが発生する場合がある。しかし、実施の形態2の銅電極26aのように、絶縁基板21側の硬度が電力用半導体素子1側の硬度よりも小さい電極を使用した場合、クラックの発生が減少することがわかった。硬度が小さい部分で応力緩和が起こるものと考えられる。
一方、実施の形態1のような構成であっても、絶縁基板21側の層を硬度が低くなるめっき条件で形成し、電力用半導体素子1側の層をメッキ液に硬化剤を加えるなどして硬度が高くなるめっき条件で形成しても同様な効果が得られるはずである。
2 回路基板(電極付絶縁基板)、
3 ベース板、
4 焼結金属結合層、
4P 焼結性銀粒子接合材(銀ナノペースト)、
5 接合材(はんだ)、
6 リード(配線材)、
7 接合材(はんだ)、
11 半導体チップ(半導体基板)、
12 金属シリサイド、
13 第1金属層、
14 第2金属層、
21 絶縁基板、
22 スパッタ膜(金属薄膜)、
23 銅めっき電極(電極)、
24 接合材(ろう材)、
26 銅電極(26B:下地銅板、26P:銅めっき層)、
PB 接合面、
百位の数字は実施の形態による違いを示す。
Claims (9)
- セラミック材料で構成された絶縁基板の一方の面に、銅材料で構成された電極が設けられた回路基板と、
前記電極に焼結性銀粒子接合材を用いて接合された半導体素子と、を備え、
前記電極は、前記半導体素子との接合面から前記絶縁基板に向かう50μmの深さまでの部分が、ビッカース硬さ70HV以上の硬度を有し、かつ、前記絶縁基板側の部分のビッカース硬さが50HV以下であることを特徴とする半導体装置。 - 前記接合面から前記絶縁基板に向かう50μmの深さまでの部分が、ビッカース硬さ100HV以上の硬度を有していることを特徴とする請求項1に記載の半導体装置。
- 前記接合面から前記絶縁基板に向かう50μmの深さまでの部分が、めっきにより形成されていることを特徴とする請求項1または2に記載の半導体装置。
- 前記半導体素子は電力用半導体素子であり、
前記電極は150μm以上の厚みを有することを特徴とする請求項1ないし3のいずれか1項に記載の半導体装置。 - 前記電力用半導体素子がワイドバンドギャップ半導体材料で形成されていることを特徴とする請求項4に記載の半導体装置。
- 前記ワイドバンドギャップ半導体材料は、炭化ケイ素、窒化ガリウム系材料、ガリウムヒ素、およびダイヤモンドのうちのいずれかであることを特徴とする請求項5に記載の半導体装置。
- セラミック材料で構成された絶縁基板の少なくとも一方の面の所定範囲に、スパッタにより金属薄膜を形成する工程と、
前記金属薄膜上に、ビッカース硬度が50HV以下となるように第1の銅のめっき層を形成する工程と、
前記第1の銅のめっき層の上に、50μm以上の厚みで、ビッカース硬度が70HV以上となるように第2の銅のめっき層を形成し、半導体素子との接合面を有する電極を形成する工程と、
前記電極の接合面に、焼結性銀粒子接合材を用いて前記半導体素子を接合する工程と、
を含む半導体装置の製造方法。 - セラミック材料で構成された絶縁基板の少なくとも一方の面に、少なくとも前記絶縁基板側の部分の接合後のビッカース硬度が50HV以下となるように、所定形状の銅板を接合する工程と、
前記絶縁基板に接合された銅板の表面に銅めっきを行い、50μm以上の厚みでビッカース硬度が70HV以上となるように半導体素子との接合面を有する電極を形成する工程と、
前記電極の接合面に、焼結性銀粒子接合材を用いて前記半導体素子を接合する工程と、
を含む半導体装置の製造方法。 - 前記形成した電極の厚みが150μm以上であることを特徴とする請求項7または8に記載の半導体装置の製造方法。
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