JP5617495B2 - 半導体装置の製造方法及び半導体装置 - Google Patents
半導体装置の製造方法及び半導体装置 Download PDFInfo
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- JP5617495B2 JP5617495B2 JP2010219570A JP2010219570A JP5617495B2 JP 5617495 B2 JP5617495 B2 JP 5617495B2 JP 2010219570 A JP2010219570 A JP 2010219570A JP 2010219570 A JP2010219570 A JP 2010219570A JP 5617495 B2 JP5617495 B2 JP 5617495B2
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- 238000004132 cross linking Methods 0.000 description 1
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- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- SUBJHSREKVAVAR-UHFFFAOYSA-N sodium;methanol;methanolate Chemical compound [Na+].OC.[O-]C SUBJHSREKVAVAR-UHFFFAOYSA-N 0.000 description 1
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- 239000008117 stearic acid Substances 0.000 description 1
- PJANXHGTPQOBST-UHFFFAOYSA-N stilbene Chemical compound C=1C=CC=CC=1C=CC1=CC=CC=C1 PJANXHGTPQOBST-UHFFFAOYSA-N 0.000 description 1
- 235000021286 stilbenes Nutrition 0.000 description 1
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- BRKFQVAOMSWFDU-UHFFFAOYSA-M tetraphenylphosphanium;bromide Chemical compound [Br-].C1=CC=CC=C1[P+](C=1C=CC=CC=1)(C=1C=CC=CC=1)C1=CC=CC=C1 BRKFQVAOMSWFDU-UHFFFAOYSA-M 0.000 description 1
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- JXUKBNICSRJFAP-UHFFFAOYSA-N triethoxy-[3-(oxiran-2-ylmethoxy)propyl]silane Chemical compound CCO[Si](OCC)(OCC)CCCOCC1CO1 JXUKBNICSRJFAP-UHFFFAOYSA-N 0.000 description 1
- ZNOCGWVLWPVKAO-UHFFFAOYSA-N trimethoxy(phenyl)silane Chemical compound CO[Si](OC)(OC)C1=CC=CC=C1 ZNOCGWVLWPVKAO-UHFFFAOYSA-N 0.000 description 1
- DQZNLOXENNXVAD-UHFFFAOYSA-N trimethoxy-[2-(7-oxabicyclo[4.1.0]heptan-4-yl)ethyl]silane Chemical compound C1C(CC[Si](OC)(OC)OC)CCC2OC21 DQZNLOXENNXVAD-UHFFFAOYSA-N 0.000 description 1
- BPSIOYPQMFLKFR-UHFFFAOYSA-N trimethoxy-[3-(oxiran-2-ylmethoxy)propyl]silane Chemical compound CO[Si](OC)(OC)CCCOCC1CO1 BPSIOYPQMFLKFR-UHFFFAOYSA-N 0.000 description 1
- YUYCVXFAYWRXLS-UHFFFAOYSA-N trimethoxysilane Chemical compound CO[SiH](OC)OC YUYCVXFAYWRXLS-UHFFFAOYSA-N 0.000 description 1
- BIKXLKXABVUSMH-UHFFFAOYSA-N trizinc;diborate Chemical compound [Zn+2].[Zn+2].[Zn+2].[O-]B([O-])[O-].[O-]B([O-])[O-] BIKXLKXABVUSMH-UHFFFAOYSA-N 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
- XOOUIPVCVHRTMJ-UHFFFAOYSA-L zinc stearate Chemical compound [Zn+2].CCCCCCCCCCCCCCCCCC([O-])=O.CCCCCCCCCCCCCCCCCC([O-])=O XOOUIPVCVHRTMJ-UHFFFAOYSA-L 0.000 description 1
- XAEWLETZEZXLHR-UHFFFAOYSA-N zinc;dioxido(dioxo)molybdenum Chemical compound [Zn+2].[O-][Mo]([O-])(=O)=O XAEWLETZEZXLHR-UHFFFAOYSA-N 0.000 description 1
Images
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H01L2924/156—Material
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
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- Compositions Of Macromolecular Compounds (AREA)
- Epoxy Resins (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
単位に切り離し後の反り)を低減されることを目的として、エポキシ樹脂成形材料のガラス転移温度、曲げ弾性率及び成形収縮率を特定範囲とすることが提案されている(例えば、「特許文献1」参照。)。
1)半導体装置のサイズが20mm×20mm以下である。
2)基板の厚みが300μm以下である。
3)基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みが600μm以下である。a)封止用エポキシ樹脂組成物が無機充填材を含むものであり、前記組成物中における無機充填材含有量が74質量%以上、86質量%以下である。
b)封止用エポキシ樹脂組成物における無機充填材含有量をx(質量%)とし、封止用エポキシ樹脂組成物を175℃、120秒で成形した際の成形収縮率をy(%)としたとき、0.032x+y−2.965の値が0.000〜0.300である。
で表される構造を有するエポキシ樹脂を含むものとすることができる。
1)半導体装置のサイズが20mm×20mm以下である。
2)基板の厚みが300μm以下である。
3)基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みが600μm以下である。a)封止用エポキシ樹脂組成物が無機充填材を含むものであり、組成物中における無機充填材含有量が74質量%以上、86質量%以下である。
b)封止用エポキシ樹脂組成物における無機充填材含有量をx(質量%)とし、封止用エポキシ樹脂組成物を175℃、120秒で成形した際の成形収縮率をy(%)としたとき、0.032x+y−2.965の値が0.000〜0.300である。
をもつ試験片を成形し、20℃での金型キャビティのリブ部内径寸法と、20℃での円盤状試験片のリブ部外径寸法とを測定し、下記式で算出する。
以下、封止用エポキシ樹脂組成物について詳細に説明する。本発明では、封止用エポキシ樹脂組成物が充填材として、無機充填材を用いる。無機充填材としては、一般に封止用エポキシ樹脂組成物に用いられているものを使用することができ、例えば、溶融シリカ、球状シリカ、結晶シリカ、アルミナ、窒化珪素、窒化アルミ等が挙げられる。無機充填材の平均粒径としては、1μm以上、20μm以下であることが好ましい。平均粒径が上記上限値以下であれば、半田バンプ等の接続部材周辺を含む半導体素子と基板との間隙部分への充填性が低下する恐れが少ない。また、平均粒径が上記下限値以上であれば、増粘によって充填性が低下する恐れが少ない。
レン;ヘキサヒドロ無水フタル酸(HHPA)、メチルテトラヒドロ無水フタル酸(MTHPA)などの脂環族酸無水物、無水トリメリット酸(TMA)、無水ピロメリット酸(PMDA)、ベンゾフェノンテトラカルボン酸(BTDA)などの芳香族酸無水物などを含む酸無水物等;ポリサルファイド、チオエステル、チオエーテルなどのポリメルカプタン化合物;イソシアネートプレポリマー、ブロック化イソシアネートなどのイソシアネート化合物;カルボン酸含有ポリエステル樹脂などの有機酸類が例示される。これらは1種類を単独で用いても2種類以上を組み合わせて用いてもよい。また、これらのうち、耐湿性、信頼性等の点から、1分子内に少なくとも2個のフェノール性水酸基を有する化合物が好ましく、フェノールノボラック樹脂、クレゾールノボラック樹脂、tert−ブチルフェノールノボラック樹脂、ノニルフェノールノボラック樹脂等のノボラック型フェノール樹脂;レゾール型フェノール樹脂;ポリパラオキシスチレン等のポリオキシスチレン;フェニレン骨格含有フェノールアラルキル樹脂、ビフェニレン骨格含有フェノールアラルキル樹脂等が例示される。
、ベンジルジメチルアミン、2−メチルイミダゾール等の窒素原子含有化合物等が挙げられる。これらのうち、リン原子含有化合物が好ましく、特に封止用エポキシ樹脂組成物の粘度を低くすることにより流動性を向上させることができること、さらに硬化立ち上がり速度という点を考慮するとテトラ置換ホスホニウム化合物が好ましく、また封止用エポキシ樹脂組成物の硬化物の熱時低弾性率という点を考慮するとホスホベタイン化合物、ホスフィン化合物とキノン化合物との付加物が好ましく、また潜伏的硬化性という点を考慮すると、ホスホニウム化合物とシラン化合物との付加物が好ましい。また、封止用エポキシ樹脂組成物がa)の要件を満たしつつb)の要件をも容易に満たすことができるとの観点からは、ホスホニウム化合物とシラン化合物との付加物、1,8−ジアザビシクロ(5,4,0)ウンデセン−7、ポスフィン化合物とキノン化合物の付加物、有機ホスフィンを用いることが好ましく、特にホスホニウム化合物とシラン化合物との付加物を用いることが好ましい。
また、一般式(2)において、X1は、Y1及びY2と結合する有機基である。同様に、X2は、Y3及びY4と結合する有機基である。Y1及びY2はプロトン供与性置換基がプロトンを放出してなる基であり、同一分子内のY1及びY2が珪素原子と結合してキレート構造を形成するものである。同様にY3及びY4はプロトン供与性置換基がプロトンを放出してなる基であり、同一分子内のY3及びY4が珪素原子と結合してキレート構造を形成するものである。X1及びX2は互いに同一でも異なっていてもよく、Y1、Y
2、Y3及びY4は互いに同一であっても異なっていてもよい。
用してもよい。
のものを示したが、2個以上が並列又は積層されて搭載された形態のものであってもよい。かかる半導体装置は、1)〜3)の要件を満たすものであり、かつ、a)、b)の要件を満たす封止用エポキシ樹脂組成物を成形することにより得られる封止樹脂硬化体6により、半田バンプ周辺を含む基板と半導体素子との間隙部分の封止と、半導体素子4のオーバーモールドが形成されているため、耐湿性等の信頼性の低下を来たすことなく、パネル反りやパッケージ反りを低減することができ、薄型化と高い信頼性の両立ができる半導体装置を経済的に得ることができる。
(無機充填材)
無機充填材1:溶融球状シリカ((株)龍森製、MUF−6。篩により24μm以上の粒子を除去したもの。平均粒径6μm、比表面積3.4m2/g。)
エポキシ樹脂1:下記式(3)で表される構造を有するエポキシ樹脂(大日本インキ(株)製、EXA−7320。o−クレゾールとホルムアルデヒドと2−メトキシナフタレンを共縮合して得られたフェノール樹脂をエピクロルヒドリンでグリシジルエーテル化したエポキシ樹脂。エポキシ当量251g/eq、軟化点58℃。下記式(3)において、m、nはモル比を表し、m/nの平均値は1/4。)
エポキシ樹脂3:トリス(ヒドロキシフェニル)メタン型エポキシ樹脂(三菱化学(株)製、1032H60。エポキシ当量170g/eq、軟化点60℃。)
硬化剤1:ビフェニレン骨格含有フェノールアラルキル樹脂(日本化薬(株)製、GPH−65、水酸基当量196g/eq、軟化点65℃。)
硬化剤2:フェニレン骨格含有フェノールアラルキル樹脂(三井化学(株)製、XLC−4L。水酸基当量165g/eq、軟化点65℃。)
硬化剤3:フェノールノボラック樹脂(住友ベークライト(株)製、PR−HF−3。水酸基当量104g/eq、軟化点80℃。)
シランカップリング剤1:N−フェニル−γ−アミノプロピルトリメトキシシラン(東レ・ダウコーニング(株)製、商品名CF−4083)
離型剤1:カルナバワックス(日興リカ(株)製、ニッコウカルナバ)
着色剤1:カーボンブラック(三菱化学(株)製、MA600)
表1及び表2の配合に従い、各原料をミキサーで混合した後、表面温度が90℃と45℃の2本ロールを用いて混練し、冷却後粉砕してエポキシ樹脂組成物を得た。得られたエポキシ樹脂組成物を以下の方法で評価した。結果を表1及び表2に示した。
スパイラルフロー:低圧トランスファー成形機(コータキ精機(株)製、KTS−15)を用いて、ANSI/ASTM D 3123−72に準じたスパイラルフロー測定用金型に、金型温度175℃、注入圧力6.9MPa、保圧時間120秒の条件でエポキシ
樹脂組成物を注入し、流動長を測定した。単位はcm。スパイラルフローは、流動性のパラメータであり、数値が大きい方が良好な流動性を示す。判定基準は100cm未満を不合格、100cm以上を合格とした。
成形収縮率(%)={(20℃での金型キャビティのリブ部内径寸法)−(20℃での円盤状試験片のリブ部外径寸法)}/(20℃での金型キャビティのリブ部内径寸法)×100(%)
時間15秒の条件で脱気成形(17torr)にて50mm×55mm×350μm厚(基板の半導体素子搭載面からの封止樹脂硬化体の最大厚み)のサイズのパネルを成形した。成形に用いた基板(コア:三菱瓦斯化学(株)製、CCL−HL832HS、100μm厚。Cu:12μ厚。レジスト:太陽インキ製造(株)製、PSR−AUS308、12μ厚。)のサイズは55mm×62mmで、あらかじめ10mm×10mm×150μm厚(半田バンプを除く)のフリップチップ(SIN表面、搭載半田バンプ:φ100μmの鉛フリー半田、200μmピッチのフルグリッド)を3×3=9個搭載してある。成
形後、ポストキュアとして175℃で4時間加熱処理し、個片化前のパネルについて、シャドーモアレ方式の反り測定装置(Acrometrix社製、PS−200)を用いて高さ方向の変位を測定し、変位差の最も大きい値をパネル反り量とした。測定温度は25℃。判定基準は、1.2mm以上を不合格、1.2mm未満を合格とした。
パネル反り量(B PKG):基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みを上記パネル反り量(A PKG)より100μm薄くして250μmとした以外は、上記パネル反り量(A PKG)と同様の処理、測定を行った。判定基準は、1.2mm以上を不合格、1.2mm未満を合格とした。
注入時間15秒の条件で脱気成形(17torr)にて50mm×55mm×350μm厚(基板の半導体素子搭載面からの封止樹脂硬化体の最大厚み)のサイズのパネルを成形した。成形に用いた基板(コア:三菱瓦斯化学(株)製、CCL−HL832HS、100μm厚。Cu:12μ厚。レジスト:太陽インキ製造(株)製、PSR−AUS308、12μ厚。)のサイズは55mm×62mmで、あらかじめ10mm×10mm×150μm厚(半田バンプを除く)のフリップチップ(SIN表面、搭載半田バンプ:φ100μmの鉛フリー半田、200μmピッチのフルグリッド)を3×3=9個搭載してある。成形後、ポストキュアとして175℃で4時間加熱処理し、14×14mmのサイズに9個切り出し、テスト用のBGAパッケージを得た。得られたパッケージ9個について、シャドーモアレ方式の反り測定装置(Acrometrix社製、PS−200)を用いて高さ方向の変位を測定し、変位差の最も大きい値をパッケージ反り量とした。測定温度は25℃。判定基準は、50μm以上を不合格、50μm未満を合格とした。
パッケージ反り量(B PKG):基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みを上記パッケージ反り量(A PKG)より100μm薄くして250μmとした以外は、上記パッケージ反り量(A PKG)と同様の処理、測定を行った。判定基準は、同様に、50μm以上を不合格、50μm未満を合格とした。
2 ソルダーレジスト
3 ダイボンド材硬化体
4 半導体素子
5 ボンディングワイヤ
6 封止樹脂硬化体
7 半田ボール
8 半田バンプ
9 ダイシングライン
Claims (6)
- 基板と、前記基板上に搭載された1個以上の半導体素子と、前記基板と前記半導体素子とを電気的に接続する接続部材と、前記半導体素子と前記接続部材とを封止する封止樹脂硬化体とを備え、かつ下記1)〜3)の要件を満たす半導体装置の製造方法であって、
前記基板に複数の半導体装置に対応する前記半導体素子を搭載し、前記半導体素子と前記接続部材とを前記封止樹脂硬化体により一括で封止した後、前記半導体装置単位に切り離しを行うことで得られ、
前記封止樹脂硬化体が、下記a)、b)の要件を満たす封止用エポキシ樹脂組成物をトランスファーモールド法、コンプレッションモールド法又はインジェクションモールド法で成形することにより得られることを特徴とする半導体装置の製造方法。
1)半導体装置のサイズが20mm×20mm以下である。
2)基板の厚みが300μm以下である。
3)基板の半導体素子搭載面からの封止樹脂硬化体の最大厚みが600μm以下である。a)封止用エポキシ樹脂組成物が無機充填材として溶融シリカを含むものであり、前記組成物中における溶融シリカの含有量が74質量%以上、86質量%以下である。
b)封止用エポキシ樹脂組成物における溶融シリカの含有量をx(質量%)とし、封止用エポキシ樹脂組成物を175℃、120秒で成形した際の成形収縮率をy(%)としたとき、0.032x+y−2.965の値が0.000〜0.300である。 - 前記封止用エポキシ樹脂組成物が下記一般式(1):
同じであっても異なっていてもよい。R1は炭素数1〜6の炭化水素基であり、互いに同じであっても異なっていてもよい。R2は炭素数1〜4の炭化水素基で、W1は酸素原子又は硫黄原子である。R3は水素、炭素数1〜4の炭化水素基又は炭素数6〜20の芳香族基であり、互いに同じであっても異なっていてもよい。aは0〜10の整数、bは1〜3の整数である。m、nはモル比を表し、0≦m<1、0<n≦1で、m+n=1、かつ、m/nの平均値は1/10〜1/1である。)
で表される構造を有するエポキシ樹脂を含むことを特徴とする請求項1記載の半導体装置の製造方法。 - 前記封止用エポキシ樹脂組成物が硬化剤としてビフェニレン骨格含有フェノールアラルキル樹脂を含むことを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記封止用エポキシ樹脂組成物が平均粒径1〜20μmの無機充填材を含むことを特徴とする請求項1ないし3のいずれか1項に記載された半導体装置の製造方法。
- 前記接続部材が半田バンプであり、前記半田バンプが形成された前記半導体素子をフェイスダウンで前記基板上に搭載し、前記半田バンプと前記基板上の電極とを電気的に接続することを特徴とする請求項1ないし4のいずれか1項に記載の半導体装置の製造方法。
- 請求項1ないし5のいずれか1項に記載の半導体装置の製造方法により得られることを特徴とする半導体装置。
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