JP5586696B2 - 直列に接続されたled用のサブマウントのツェナーダイオード保護ネットワーク - Google Patents
直列に接続されたled用のサブマウントのツェナーダイオード保護ネットワーク Download PDFInfo
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
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- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/40—Details of LED load circuits
- H05B45/44—Details of LED load circuits with an active control inside an LED matrix
- H05B45/48—Details of LED load circuits with an active control inside an LED matrix having LEDs organised in strings and incorporating parallel shunting devices
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
- H05B45/54—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits in a series array of LEDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
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Description
Claims (15)
- 電極及び半導体光放射表面を持つ直列に接続されたN個のフリップチップ発光ダイオード(LED)であって、Nは2以上であり、LED間の各接続部にノードがあり、第1の電源端子に接続されたアノードを持つ第1端部LED及び第2の電源端子に接続されたカソードを持つ第2端部LEDを有する当該LEDと、第1端部LEDの前記アノードに接続された第1端部ツェナーダイオード、第2端部LEDの前記カソードに接続された第2端部ツェナーダイオード、及びLED間の各接続部でノード毎に当該ノードに接続されたたった1つの中間のツェナーダイオードを有する、N個のLEDに接続された過渡電圧抑制回路とを有し、
第1端部LEDの前記アノードに接続された第1端部ツェナーダイオード、第2端部LEDの前記カソードに接続された第2端部ツェナーダイオード、及びノード毎に当該ノードに接続された前記中間のツェナーダイオードをシリコンサブマウントの表面に形成した、N個のLEDが取り付けられる当該シリコンサブマウントであって、前記シリコンサブマウントはp+タイプであり、各ツェナーダイオードは前記シリコンサブマウントの表面のn+領域により形成される、前記シリコンサブマウントを更に有する、光放射装置。 - 前記シリコンサブマウントの上部表面上に形成されたパターン化された金属層を更に有し、前記パターン化された金属層は、全てのLEDを直列に相互接続し、前記ツェナーダイオードを前記LEDの電極に接続する、請求項1に記載の光放射装置。
- 前記LEDの前記半導体光放射表面の光−電気化学的(PEC)エッチングの間、前記LEDの前記半導体光放射表面をバイアスするためバイアス電圧を受けるためのp+タイプの前記シリコンサブマウントに電気的に結合された金属コンタクト部を更に有する、請求項2に記載の光放射装置。
- 前記LEDの前記半導体光放射表面がPECエッチングによりエッチングされた、請求項3に記載の光放射装置。
- Nが3より大きく、複数の中間のツェナーダイオードがあり、隣接する中間のツェナーダイオードに対するn+領域が距離d1だけ間隔を置かれ、第1端部ツェナーダイオード及び第2端部ツェナーダイオードに対するn+領域が、d1より大きい距離d2だけ間隔を置かれる、請求項2に記載の光放射装置。
- 距離d1及びd2は、前記中間のツェナーダイオードが前記光放射装置の通常の動作電圧で電流漏れがないように、選択される、請求項5に記載の光放射装置。
- 前記N個のLEDに対する前記過渡電圧抑制回路にN+1個だけのツェナーダイオードがある、請求項2に記載の光放射装置。
- 前記N個のLEDが単一のダイに形成された接合絶縁LEDであり、前記LEDの電極の全てが、前記シリコンサブマウントに対向している前記LEDの底部表面上に形成されている、請求項2に記載の光放射装置。
- 第1端部ツェナーダイオード及び第2端部ツェナーダイオードのn+領域が、各中間のツェナーダイオードのn+領域より広い、請求項2に記載の光放射装置。
- 中間のツェナーダイオードの各n+領域が、2つのLEDの電極を直列に相互接続する、請求項2に記載の光放射装置。
- 前記N個のLEDがLEDのアレイを有する、請求項2に記載の光放射装置。
- 第1端部ツェナーダイオード及び第2端部ツェナーダイオードの対が、直列に接続された一連のN個のLEDの通常の動作電圧を超える降伏電圧を持ち、前記中間のツェナーダイオードの少なくとも幾つかは、直列に接続された一連のN個のLEDの通常の動作電圧より下の降伏電圧を持つ、請求項2に記載の光放射装置。
- 前記中間のツェナーダイオードのn+領域が前記N個のLEDの下に形成され、第1端部ツェナーダイオード及び第2端部ツェナーダイオードのn+領域の大部分は、前記N個のLEDの下に形成されていない、請求項2に記載の光放射装置。
- 前記N個のLEDが単一のダイに形成され、全ての中間のツェナーダイオードが、直列に接続された前記N個のLED間の最大動作電圧に等しい第1の電圧に絶縁破壊なしに耐えるために必要とされるよりも小さな隣接し合う中間のツェナーダイオード間の距離を持って前記ダイの下に形成され、第1端部ツェナーダイオード及び第2端部ツェナーダイオードの少なくとも一部が前記ダイの境界を越えて延在する、請求項2に記載の光放射装置。
- 電極及び半導体光放射表面を持つ直列に接続されたN個のフリップチップ発光ダイオード(LED)であって、Nは3以上であり、LED間の各接続部にノードがあり、第1の電源端子に接続されたアノードを持つ第1端部LED及び第2の電源端子に接続されたカソードを持つ第2端部LEDを有する当該LEDをシリコンサブマウントに供給する供給ステップであって、第1端部LEDのアノードに接続された第1端部ツェナーダイオード、第2端部LEDのカソードに接続された第2端部ツェナーダイオード、及びLED間の各接続部でノード毎に当該ノードに接続されたたった1つの中間のツェナーダイオードを有するN個のLEDに接続された、過渡電圧抑制回路を前記シリコンサブマウントに形成し、当該シリコンサブマウントはp+タイプであり、各ツェナーダイオードは当該シリコンサブマウントの表面のn+領域により形成され、パターン化された金属層が前記シリコンサブマウントの上部表面上に形成され、前記パターン化された金属層は、全てのLEDを直列に相互接続し、前記ツェナーダイオードを前記LEDの電極に接続する、前記供給ステップと、p+タイプの物質及びツェナーダイオードを介して前記N個のLEDの前記半導体光放射表面を電気的にバイアスするためにバイアス電圧を前記シリコンサブマウントの前記p+タイプの物質に付与するステップと、電解溶液に前記半導体光放射表面を浸すステップと、前記半導体光放射表面のフォト電気化学的エッチング(PEC)を実施するステップとを有する、方法。
Applications Claiming Priority (3)
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US12/556,054 | 2009-09-09 | ||
US12/556,054 US8400064B2 (en) | 2009-09-09 | 2009-09-09 | Zener diode protection network in submount for LEDs connected in series |
PCT/IB2010/053773 WO2011030252A1 (en) | 2009-09-09 | 2010-08-20 | Zener diode protection network in submount for leds connected in series |
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JP2013504868A JP2013504868A (ja) | 2013-02-07 |
JP5586696B2 true JP5586696B2 (ja) | 2014-09-10 |
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EP (1) | EP2476294B1 (ja) |
JP (1) | JP5586696B2 (ja) |
KR (1) | KR101662358B1 (ja) |
CN (1) | CN102484920B (ja) |
TW (1) | TWI514926B (ja) |
WO (1) | WO2011030252A1 (ja) |
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2009
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US20110057569A1 (en) | 2011-03-10 |
US8400064B2 (en) | 2013-03-19 |
JP2013504868A (ja) | 2013-02-07 |
CN102484920A (zh) | 2012-05-30 |
TW201117653A (en) | 2011-05-16 |
KR20120066652A (ko) | 2012-06-22 |
EP2476294A1 (en) | 2012-07-18 |
TWI514926B (zh) | 2015-12-21 |
WO2011030252A1 (en) | 2011-03-17 |
EP2476294B1 (en) | 2013-12-25 |
KR101662358B1 (ko) | 2016-10-10 |
CN102484920B (zh) | 2015-11-25 |
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