JP5572347B2 - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP5572347B2
JP5572347B2 JP2009201771A JP2009201771A JP5572347B2 JP 5572347 B2 JP5572347 B2 JP 5572347B2 JP 2009201771 A JP2009201771 A JP 2009201771A JP 2009201771 A JP2009201771 A JP 2009201771A JP 5572347 B2 JP5572347 B2 JP 5572347B2
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Japan
Prior art keywords
single crystal
substrate
crystal semiconductor
semiconductor substrate
insulating layer
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Expired - Fee Related
Application number
JP2009201771A
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English (en)
Japanese (ja)
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JP2010087492A (ja
JP2010087492A5 (https=
Inventor
佑太 遠藤
良太 今林
良介 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2009201771A priority Critical patent/JP5572347B2/ja
Publication of JP2010087492A publication Critical patent/JP2010087492A/ja
Publication of JP2010087492A5 publication Critical patent/JP2010087492A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes

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  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
JP2009201771A 2008-09-05 2009-09-01 Ｓｏｉ基板の作製方法 Expired - Fee Related JP5572347B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009201771A JP5572347B2 (ja) 2008-09-05 2009-09-01 Ｓｏｉ基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008227725 2008-09-05
JP2008227725 2008-09-05
JP2009201771A JP5572347B2 (ja) 2008-09-05 2009-09-01 Ｓｏｉ基板の作製方法

Publications (3)

Publication Number Publication Date
JP2010087492A JP2010087492A (ja) 2010-04-15
JP2010087492A5 JP2010087492A5 (https=) 2012-10-11
JP5572347B2 true JP5572347B2 (ja) 2014-08-13

Family

ID=41799628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009201771A Expired - Fee Related JP5572347B2 (ja) 2008-09-05 2009-09-01 Ｓｏｉ基板の作製方法

Country Status (3)

Country Link
US (1) US8187953B2 (https=)
JP (1) JP5572347B2 (https=)
SG (1) SG159484A1 (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5364345B2 (ja) * 2008-11-12 2013-12-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8318588B2 (en) * 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
SG178179A1 (en) * 2009-10-09 2012-03-29 Semiconductor Energy Lab Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate
US8367519B2 (en) * 2009-12-30 2013-02-05 Memc Electronic Materials, Inc. Method for the preparation of a multi-layered crystalline structure
EP2532773A4 (en) * 2010-02-05 2013-12-11 Sumitomo Electric Industries METHOD FOR PRODUCING A SILICON CARBIDE SUBSTRATE
US9287353B2 (en) 2010-11-30 2016-03-15 Kyocera Corporation Composite substrate and method of manufacturing the same
AU2011337629A1 (en) * 2010-11-30 2013-05-02 Kyocera Corporation Composite substrate and production method
TWI570809B (zh) * 2011-01-12 2017-02-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
US9123529B2 (en) 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
CN106409650B (zh) * 2015-08-03 2019-01-29 沈阳硅基科技有限公司 一种硅片直接键合方法
KR20190027821A (ko) * 2016-07-12 2019-03-15 큐맷, 인코포레이티드 재생을 거친 도너 기판의 방법
WO2018011731A1 (en) * 2016-07-12 2018-01-18 QMAT, Inc. Method of a donor substrate undergoing reclamation
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
US11289330B2 (en) 2019-09-30 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator (SOI) substrate and method for forming
FR3163205A1 (fr) * 2024-06-10 2025-12-12 Soitec Procédé de fabrication d’une plaquette donneuse pour le transfert de couches minces, et plaquette donneuse

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1140786A (ja) * 1997-07-18 1999-02-12 Denso Corp 半導体基板及びその製造方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2000223682A (ja) 1999-02-02 2000-08-11 Canon Inc 基体の処理方法及び半導体基板の製造方法
JP2000349266A (ja) 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
FR2834123B1 (fr) 2001-12-21 2005-02-04 Soitec Silicon On Insulator Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report
TWI233154B (en) 2002-12-06 2005-05-21 Soitec Silicon On Insulator Method for recycling a substrate
JP5284576B2 (ja) * 2006-11-10 2013-09-11 信越化学工業株式会社 半導体基板の製造方法

Also Published As

Publication number Publication date
US20100062546A1 (en) 2010-03-11
JP2010087492A (ja) 2010-04-15
SG159484A1 (en) 2010-03-30
US8187953B2 (en) 2012-05-29

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