JP5541618B2 - 半導体パッケージの製造方法 - Google Patents

半導体パッケージの製造方法 Download PDF

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Publication number
JP5541618B2
JP5541618B2 JP2009201299A JP2009201299A JP5541618B2 JP 5541618 B2 JP5541618 B2 JP 5541618B2 JP 2009201299 A JP2009201299 A JP 2009201299A JP 2009201299 A JP2009201299 A JP 2009201299A JP 5541618 B2 JP5541618 B2 JP 5541618B2
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JP
Japan
Prior art keywords
semiconductor chip
layer
resin portion
semiconductor
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009201299A
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English (en)
Japanese (ja)
Other versions
JP2011054703A5 (https=
JP2011054703A (ja
Inventor
晃明 千野
昭彦 立岩
史雅 片桐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009201299A priority Critical patent/JP5541618B2/ja
Priority to US12/839,473 priority patent/US8436471B2/en
Publication of JP2011054703A publication Critical patent/JP2011054703A/ja
Publication of JP2011054703A5 publication Critical patent/JP2011054703A5/ja
Application granted granted Critical
Publication of JP5541618B2 publication Critical patent/JP5541618B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2009201299A 2009-09-01 2009-09-01 半導体パッケージの製造方法 Expired - Fee Related JP5541618B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009201299A JP5541618B2 (ja) 2009-09-01 2009-09-01 半導体パッケージの製造方法
US12/839,473 US8436471B2 (en) 2009-09-01 2010-07-20 Semiconductor package with its surface edge covered by resin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009201299A JP5541618B2 (ja) 2009-09-01 2009-09-01 半導体パッケージの製造方法

Publications (3)

Publication Number Publication Date
JP2011054703A JP2011054703A (ja) 2011-03-17
JP2011054703A5 JP2011054703A5 (https=) 2012-09-13
JP5541618B2 true JP5541618B2 (ja) 2014-07-09

Family

ID=43623633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009201299A Expired - Fee Related JP5541618B2 (ja) 2009-09-01 2009-09-01 半導体パッケージの製造方法

Country Status (2)

Country Link
US (1) US8436471B2 (https=)
JP (1) JP5541618B2 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5581519B2 (ja) * 2009-12-04 2014-09-03 新光電気工業株式会社 半導体パッケージとその製造方法
US10418298B2 (en) * 2013-09-24 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual fan-out semiconductor package
US10032704B2 (en) * 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US20170133334A1 (en) * 2015-11-09 2017-05-11 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
JP6921794B2 (ja) * 2018-09-14 2021-08-18 株式会社東芝 半導体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3726318B2 (ja) * 1995-08-22 2005-12-14 株式会社日立製作所 チップ サイズ パッケージとその製造方法及びセカンド レヴェル パッケージング
TW351008B (en) * 1996-12-24 1999-01-21 Matsushita Electronics Corp Lead holder, manufacturing method of lead holder, semiconductor and manufacturing method of semiconductor
JP2000124354A (ja) * 1998-10-21 2000-04-28 Matsushita Electric Ind Co Ltd チップサイズパッケージ及びその製造方法
US6348728B1 (en) * 2000-01-28 2002-02-19 Fujitsu Limited Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
AU2001283257A1 (en) 2000-08-16 2002-02-25 Intel Corporation Direct build-up layer on an encapsulated die package
JP2004079716A (ja) * 2002-08-14 2004-03-11 Nec Electronics Corp 半導体用ｃｓｐ型パッケージ及びその製造方法
JP4549171B2 (ja) * 2004-08-31 2010-09-22 三洋電機株式会社 混成集積回路装置
WO2006100768A1 (ja) * 2005-03-23 2006-09-28 Fujitsu Limited 半導体装置及びその製造方法
CN100539054C (zh) * 2007-03-13 2009-09-09 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法

Also Published As

Publication number Publication date
US20110049726A1 (en) 2011-03-03
JP2011054703A (ja) 2011-03-17
US8436471B2 (en) 2013-05-07

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