JP5524167B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5524167B2 JP5524167B2 JP2011266116A JP2011266116A JP5524167B2 JP 5524167 B2 JP5524167 B2 JP 5524167B2 JP 2011266116 A JP2011266116 A JP 2011266116A JP 2011266116 A JP2011266116 A JP 2011266116A JP 5524167 B2 JP5524167 B2 JP 5524167B2
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Description
13…フローティングゲート電極膜 14…素子分離領域
15…電極間絶縁膜 16…コントロールゲート電極膜
21…マスク膜
21a、21b…マスクパターン(第1のマスクパターン)
21c…ダミーラインパターン
22…ハードマスク膜 22a、22b…ハードマスクパターン
23a、23b、24、24c、26…フォトレジストパターン
25c…側壁マスクパターン(第2のマスクパターン)
25a、25b…側壁マスクパターン
25ap、25bp、25cp…所定マスク部分
Claims (1)
- メモリセルアレイ領域及び周辺回路領域内の下地領域上に、第1のマスク材を形成する工程と、
第1のピッチで配置された複数のダミーラインパターンを、前記メモリセルアレイ領域内の前記第1のマスク材から形成する工程と、
複数の所定線幅をそれぞれ有する複数の第1のマスクパターンを、前記周辺回路領域内の前記第1のマスク材を用い、且つ、前記第1のマスク材の上面上に前記第1のマスク材のエッチングに対する保護マスクを設けて形成する工程と、
前記ダミーラインパターンの両長側面に形成された所定マスク部分を有し、前記ダミーラインパターンを囲む閉ループ形状の第2のマスクパターンを形成する工程と、
前記ダミーラインパターンを除去し、前記保護マスクを含む前記第1のマスクパターン及び前記第2のマスクパターンを残す工程と、
前記閉ループ形状の第2のマスクパターンの両端部分を除去して前記所定マスク部分を残す工程と、
前記所定マスク部分及び前記第1のマスクパターンをマスクとして用いて前記下地領域をエッチングする工程と、
を備えたことを特徴とする半導体装置の製造方法。
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JP2011266116A JP5524167B2 (ja) | 2011-12-05 | 2011-12-05 | 半導体装置の製造方法 |
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JP2011266116A JP5524167B2 (ja) | 2011-12-05 | 2011-12-05 | 半導体装置の製造方法 |
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JP2005119864A Division JP4921723B2 (ja) | 2005-04-18 | 2005-04-18 | 半導体装置の製造方法 |
Publications (2)
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JP2012094880A JP2012094880A (ja) | 2012-05-17 |
JP5524167B2 true JP5524167B2 (ja) | 2014-06-18 |
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JP2011266116A Active JP5524167B2 (ja) | 2011-12-05 | 2011-12-05 | 半導体装置の製造方法 |
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Families Citing this family (1)
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US8981446B2 (en) | 2013-03-22 | 2015-03-17 | Takashi Nakazawa | Magnetic memory and manufacturing method thereof |
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JPH0855920A (ja) * | 1994-08-15 | 1996-02-27 | Toshiba Corp | 半導体装置の製造方法 |
US6664582B2 (en) * | 2002-04-12 | 2003-12-16 | International Business Machines Corporation | Fin memory cell and method of fabrication |
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