JP5495303B2 - 半導体モジュール及び半導体モジュールの検査方法 - Google Patents
半導体モジュール及び半導体モジュールの検査方法 Download PDFInfo
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- JP5495303B2 JP5495303B2 JP2009252825A JP2009252825A JP5495303B2 JP 5495303 B2 JP5495303 B2 JP 5495303B2 JP 2009252825 A JP2009252825 A JP 2009252825A JP 2009252825 A JP2009252825 A JP 2009252825A JP 5495303 B2 JP5495303 B2 JP 5495303B2
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- Prior art keywords
- hole
- probe pin
- semiconductor
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- printed circuit
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- 239000004065 semiconductor Substances 0.000 title claims description 83
- 238000007689 inspection Methods 0.000 title claims description 39
- 238000000034 method Methods 0.000 title claims description 25
- 239000000523 sample Substances 0.000 claims description 53
- 229910000679 solder Inorganic materials 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 39
- 239000004020 conductor Substances 0.000 claims 1
- 230000007547 defect Effects 0.000 description 9
- 238000005476 soldering Methods 0.000 description 8
- 230000007246 mechanism Effects 0.000 description 6
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Description
2 プリント基板スルーホール(Pri−スルーホール)
3 パッケージ基板スルーホール(Pac−スルーホール)
6 第1プローブピン
7 第2プローブピン
10 半導体パッケージ
11 半導体チップ
12 パッケージ基板
13 ボンディングワイヤ
14 上層配線
15 下層配線
16 上部パッド
17 半田ボール
18 モール度樹脂
30 半導体パッケージ。
31 リード
50 半導体モジュール
51 プリント基板
52 上面配線
53 基板内配線
54 下部パッド
Claims (6)
- プリント基板上に半導体パッケージが搭載された半導体モジュールであって、
前記半導体パッケージは、半導体チップと、前記半導体チップを搭載したパッケージ基板と、前記パッケージ基板の露出面に配設され、外部端子として機能する導電性接合部材とを備え、
前記半導体チップと、前記導電性接合部材は、前記パッケージ基板に設けられたスルーホールを介して電気的に接続されており、
前記パッケージ基板に設けられたスルーホールと、これに電気的に接続される前記導電性接合部材の少なくとも一部は、平面視上、重畳した位置に配置されないように形成され、
前記プリント基板には、プローブピンを当該プリント基板側から貫通させて前記パッケージ基板に設けられたスルーホールに接触可能な貫通穴が形成されており、
前記パッケージ基板に設けられたスルーホールと接触させる前記プローブピンと協同して前記導電性接合部材の抵抗値を測定可能な別のプローブピンを接触させるスルーホールが、前記プリント基板に設けられている半導体モジュール。 - 前記導電性接合部材は、半田ボールであることを特徴とする請求項1に記載の半導体モジュール。
- 前記貫通穴は、プローブピン貫通型スルーホールであることを特徴とする請求項1又は2に記載の半導体モジュール。
- プリント基板上に半導体パッケージが搭載された半導体モジュールの検査方法であって、
前記半導体パッケージは、半導体チップと、前記半導体チップを搭載したパッケージ基板と、前記パッケージ基板の露出面に配設され、外部端子として機能する導電性接合部材とを備え、
前記半導体チップと、前記導電性接合部材は、前記パッケージ基板に設けられたスルーホールを介して電気的に接続されており、
前記パッケージ基板に設けられたスルーホールと、これに電気的に接続される前記導電性接合部材の少なくとも一部は、平面視上、重畳した位置に配置されないように形成され、
前記プリント基板には、プローブピンを当該プリント基板側から貫通させて前記パッケージ基板に設けられたスルーホールに接触可能な貫通穴が形成されており、
前記半導体モジュールに対して、
第1プローブピンを前記プリント基板の貫通穴に挿入して、前記パッケージ基板に設けられたスルーホールに接触させ、
第2プローブピンを、前記第1プローブピンの試験対象である前記導電性接合部材と電気的に接続されており、前記第1プローブピンと協同して抵抗値を測定可能ないずれかの導電部に接触させ、
測定された抵抗値により前記導電性接合部材の接合の良否を判定する半導体モジュールの検査方法。 - 前記導電性接合部材は、半田ボールであることを特徴とする請求項4に記載の半導体モジュールの検査方法。
- 前記貫通穴は、プローブピン貫通型スルーホールであることを特徴とする請求項4又は5に記載の半導体モジュールの検査方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009252825A JP5495303B2 (ja) | 2009-11-04 | 2009-11-04 | 半導体モジュール及び半導体モジュールの検査方法 |
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Application Number | Priority Date | Filing Date | Title |
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JP2009252825A JP5495303B2 (ja) | 2009-11-04 | 2009-11-04 | 半導体モジュール及び半導体モジュールの検査方法 |
Publications (2)
Publication Number | Publication Date |
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JP2011100763A JP2011100763A (ja) | 2011-05-19 |
JP5495303B2 true JP5495303B2 (ja) | 2014-05-21 |
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JP2009252825A Expired - Fee Related JP5495303B2 (ja) | 2009-11-04 | 2009-11-04 | 半導体モジュール及び半導体モジュールの検査方法 |
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JP (1) | JP5495303B2 (ja) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10177038A (ja) * | 1996-12-19 | 1998-06-30 | Sony Corp | 電子部品の試験用の電気的接続装置 |
JPH1172534A (ja) * | 1997-08-28 | 1999-03-16 | Mitsubishi Electric Corp | テスト端子付き半導体装置およびicソケット |
JP2002313998A (ja) * | 2002-04-04 | 2002-10-25 | Fujitsu Ltd | 半導体装置 |
JP2005251833A (ja) * | 2004-03-02 | 2005-09-15 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2008089536A (ja) * | 2006-10-05 | 2008-04-17 | Mitsubishi Electric Corp | 集積回路装置の接続検査装置 |
JP2008182264A (ja) * | 2008-03-18 | 2008-08-07 | Matsushita Electric Ind Co Ltd | 半導体装置、その製造方法およびその検査方法 |
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JP2011100763A (ja) | 2011-05-19 |
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