JP5443151B2 - 複合基板の製造方法 - Google Patents
複合基板の製造方法 Download PDFInfo
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- JP5443151B2 JP5443151B2 JP2009292329A JP2009292329A JP5443151B2 JP 5443151 B2 JP5443151 B2 JP 5443151B2 JP 2009292329 A JP2009292329 A JP 2009292329A JP 2009292329 A JP2009292329 A JP 2009292329A JP 5443151 B2 JP5443151 B2 JP 5443151B2
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- optical device
- sapphire substrate
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- 239000000758 substrate Substances 0.000 title claims description 186
- 239000002131 composite material Substances 0.000 title claims description 71
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 229910052594 sapphire Inorganic materials 0.000 claims description 80
- 239000010980 sapphire Substances 0.000 claims description 80
- 230000003287 optical effect Effects 0.000 claims description 69
- 238000000034 method Methods 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- -1 gallium nitride compound Chemical class 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/641—Heat extraction or cooling elements characterized by the materials
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
なお、光デバイスウエーハを構成するサファイア基板の表面に形成された光デバイス層の表面にヒートシンク基板を接合し、サファイア基板を所定の厚みに研削した後に、光デバイスウエーハをヒートシンク基板とともに切断することによりヒートシンクが接合された光デバイスを効率的に生産することができるが、次のような問題がある。即ち、光デバイスウエーハを構成するサファイア基板の表面に形成された光デバイス層の表面にヒートシンク基板を接合金属層を介して接合した複合基板においては、サファイア基板と接合金属層およびヒートシンク基板の厚みがそれぞれ均一に形成されていないと、研削装置のチャックテーブル上にヒートシンク基板側を保持してサファイア基板の裏面を研削し、サファイア基板を均一の厚みに加工することができない。この結果、サファイア基板の厚みを10μm程度に薄く加工すると、光デバイス層が一部露出して光デバイスの品質を低下させるとともに、光デバイスの品質の安定化が図れないという問題がある。
サファイア基板を研削してサファイア基板の厚みを均一に形成するサファイア基板厚み均一化工程と、
該サファイア基板厚み均一化工程が実施されたサファイア基板の表面に光デバイス層を形成する光デバイス層形成工程と、
サファイア基板の表面に形成された光デバイス層の表面にヒートシンク基板の表面を接合金属層を介して接合することにより複合基板を形成する複合基板形成工程と、
該複合基板のサファイア基板側を研削装置のチャックテーブルに保持してヒートシンク基板の裏面を研削し、複合基板の厚みを均一に形成する複合基板厚み均一化工程と、
該複合基板厚み均一化工程が実施された複合基板のヒートシンク基板側を研削装置のチャックテーブルに保持してサファイア基板の裏面を研削し、サファイア基板を所定の厚みに形成する仕上げ研削工程と、を含む、
ことを特徴とする複合基板の製造方法が提供される。
図1には、複合基板を構成する光デバイスウエーハを形成するための円形状のサファイア基板20が示されている。このサファイア基板20は、例えば厚みが480μmに形成されている。
20:サファイア基板
21:光デバイス層(エピ層)
3:保護テープ
4:研削装置
41:研削装置のチャックテーブル
424:研削ホイール
426:研削砥石
5:研磨装置
51:研磨装置のチャックテーブル
526:研磨パッド
Claims (1)
- サファイア基板の表面に光デバイス層が積層された光デバイスウエーハにおける光デバイス層の表面にヒートシンク基板が接合された複合基板の製造方法であって、
サファイア基板を研削してサファイア基板の厚みを均一に形成するサファイア基板厚み均一化工程と、
該サファイア基板厚み均一化工程が実施されたサファイア基板の表面に光デバイス層を形成する光デバイス層形成工程と、
サファイア基板の表面に形成された光デバイス層の表面にヒートシンク基板の表面を接合金属層を介して接合することにより複合基板を形成する複合基板形成工程と、
該複合基板のサファイア基板側を研削装置のチャックテーブルに保持してヒートシンク基板の裏面を研削し、複合基板の厚みを均一に形成する複合基板厚み均一化工程と、
該複合基板厚み均一化工程が実施された複合基板のヒートシンク基板側を研削装置のチャックテーブルに保持してサファイア基板の裏面を研削し、サファイア基板を所定の厚みに形成する仕上げ研削工程と、を含む、
ことを特徴とする複合基板の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009292329A JP5443151B2 (ja) | 2009-12-24 | 2009-12-24 | 複合基板の製造方法 |
CN201010563058.9A CN102130017B (zh) | 2009-12-24 | 2010-11-25 | 复合基板的制造方法 |
US12/968,787 US8104665B2 (en) | 2009-12-24 | 2010-12-15 | Manufacturing method for composite substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009292329A JP5443151B2 (ja) | 2009-12-24 | 2009-12-24 | 複合基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011134849A JP2011134849A (ja) | 2011-07-07 |
JP5443151B2 true JP5443151B2 (ja) | 2014-03-19 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009292329A Active JP5443151B2 (ja) | 2009-12-24 | 2009-12-24 | 複合基板の製造方法 |
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US (1) | US8104665B2 (ja) |
JP (1) | JP5443151B2 (ja) |
CN (1) | CN102130017B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9935232B2 (en) | 2015-03-12 | 2018-04-03 | Toshiba Memory Corporation | Method of manufacturing semiconductor device |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5508120B2 (ja) * | 2010-04-28 | 2014-05-28 | 株式会社ディスコ | 硬質基板の加工方法 |
US9266220B2 (en) | 2011-12-30 | 2016-02-23 | Saint-Gobain Abrasives, Inc. | Abrasive articles and method of forming same |
JP2015230971A (ja) * | 2014-06-05 | 2015-12-21 | 株式会社ディスコ | 積層ウェーハの形成方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6092686A (ja) | 1983-10-26 | 1985-05-24 | Sumitomo Electric Ind Ltd | 半導体レ−ザ−装置 |
JP2859478B2 (ja) | 1991-12-12 | 1999-02-17 | 日亜化学工業 株式会社 | 発光デバイス用の窒化ガリウム系化合物半導体ウエハーの切断方法 |
JP4060511B2 (ja) * | 2000-03-28 | 2008-03-12 | パイオニア株式会社 | 窒化物半導体素子の分離方法 |
US7033858B2 (en) * | 2003-03-18 | 2006-04-25 | Crystal Photonics, Incorporated | Method for making Group III nitride devices and devices produced thereby |
US20060124941A1 (en) * | 2004-12-13 | 2006-06-15 | Lee Jae S | Thin gallium nitride light emitting diode device |
US20060289892A1 (en) * | 2005-06-27 | 2006-12-28 | Lee Jae S | Method for preparing light emitting diode device having heat dissipation rate enhancement |
US7829909B2 (en) * | 2005-11-15 | 2010-11-09 | Verticle, Inc. | Light emitting diodes and fabrication methods thereof |
US7435664B2 (en) * | 2006-06-30 | 2008-10-14 | Intel Corporation | Wafer-level bonding for mechanically reinforced ultra-thin die |
JP2008182015A (ja) * | 2007-01-24 | 2008-08-07 | Disco Abrasive Syst Ltd | ウエーハの研削方法 |
JP2008235398A (ja) * | 2007-03-19 | 2008-10-02 | Disco Abrasive Syst Ltd | デバイスの製造方法 |
JP2008235650A (ja) * | 2007-03-22 | 2008-10-02 | Disco Abrasive Syst Ltd | デバイスの製造方法 |
JP2009043931A (ja) * | 2007-08-08 | 2009-02-26 | Disco Abrasive Syst Ltd | ウェーハの裏面研削方法 |
JP2009224454A (ja) * | 2008-03-14 | 2009-10-01 | Disco Abrasive Syst Ltd | 光デバイスの製造方法 |
-
2009
- 2009-12-24 JP JP2009292329A patent/JP5443151B2/ja active Active
-
2010
- 2010-11-25 CN CN201010563058.9A patent/CN102130017B/zh active Active
- 2010-12-15 US US12/968,787 patent/US8104665B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9935232B2 (en) | 2015-03-12 | 2018-04-03 | Toshiba Memory Corporation | Method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US20110155791A1 (en) | 2011-06-30 |
CN102130017B (zh) | 2015-09-23 |
US8104665B2 (en) | 2012-01-31 |
CN102130017A (zh) | 2011-07-20 |
JP2011134849A (ja) | 2011-07-07 |
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