JP5431752B2 - 半導体集積回路装置の製造方法 - Google Patents
半導体集積回路装置の製造方法 Download PDFInfo
- Publication number
- JP5431752B2 JP5431752B2 JP2009051667A JP2009051667A JP5431752B2 JP 5431752 B2 JP5431752 B2 JP 5431752B2 JP 2009051667 A JP2009051667 A JP 2009051667A JP 2009051667 A JP2009051667 A JP 2009051667A JP 5431752 B2 JP5431752 B2 JP 5431752B2
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- Prior art keywords
- film
- gas
- titanium
- chamber
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
- H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
- H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
- H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/20—Cleaning during device manufacture
- H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
- H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
- H10P72/0468—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
- H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/045—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/0698—Local interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0402—Apparatus for fluid treatment
- H10P72/0406—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009051667A JP5431752B2 (ja) | 2009-03-05 | 2009-03-05 | 半導体集積回路装置の製造方法 |
| US12/714,491 US7964500B2 (en) | 2009-03-05 | 2010-02-27 | Method of manufacturing semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009051667A JP5431752B2 (ja) | 2009-03-05 | 2009-03-05 | 半導体集積回路装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010206057A JP2010206057A (ja) | 2010-09-16 |
| JP2010206057A5 JP2010206057A5 (https=) | 2012-03-29 |
| JP5431752B2 true JP5431752B2 (ja) | 2014-03-05 |
Family
ID=42678640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009051667A Expired - Fee Related JP5431752B2 (ja) | 2009-03-05 | 2009-03-05 | 半導体集積回路装置の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7964500B2 (https=) |
| JP (1) | JP5431752B2 (https=) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5358165B2 (ja) * | 2008-11-26 | 2013-12-04 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
| JP6025190B2 (ja) * | 2012-06-12 | 2016-11-16 | シナプティクス・ジャパン合同会社 | Sram |
| CN103730468B (zh) * | 2012-10-16 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法、sram存储单元、sram存储器 |
| US9431509B2 (en) * | 2012-12-31 | 2016-08-30 | Texas Instruments Incorporated | High-K metal gate |
| US9887160B2 (en) * | 2015-09-24 | 2018-02-06 | International Business Machines Corporation | Multiple pre-clean processes for interconnect fabrication |
| US10510851B2 (en) * | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low resistance contact method and structure |
| US10304728B2 (en) * | 2017-05-01 | 2019-05-28 | Advanced Micro Devices, Inc. | Double spacer immersion lithography triple patterning flow and method |
| US10714334B2 (en) * | 2017-11-28 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive feature formation and structure |
| US11195923B2 (en) * | 2018-12-21 | 2021-12-07 | Applied Materials, Inc. | Method of fabricating a semiconductor device having reduced contact resistance |
| WO2021231122A1 (en) * | 2020-05-09 | 2021-11-18 | Lam Research Corporation | Methods to improve wafer wettability for plating - enhancement through sensors and control algorithms |
| KR20230013064A (ko) * | 2020-05-22 | 2023-01-26 | 램 리써치 코포레이션 | 유전체 표면들의 습식 작용화 |
| CN114420670B (zh) * | 2020-10-28 | 2024-10-29 | 上海华力集成电路制造有限公司 | 通孔及其制造方法 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001102345A (ja) | 1999-09-27 | 2001-04-13 | Jun Kikuchi | 表面処理方法および装置 |
| KR100492155B1 (ko) * | 2002-08-08 | 2005-06-01 | 삼성전자주식회사 | 반도체 소자의 실리사이드막 형성방법 |
| KR100735938B1 (ko) * | 2004-04-09 | 2007-07-06 | 동경 엘렉트론 주식회사 | Ti막 및 TiN막의 성막 방법, 접촉 구조체 및 컴퓨터 판독 가능한 기억 매체 |
| DE102005052001B4 (de) * | 2005-10-31 | 2015-04-30 | Advanced Micro Devices, Inc. | Halbleiterbauelement mit einem Kontaktpfropfen auf Kupferbasis und ein Verfahren zur Herstellung desselben |
| JP2007214538A (ja) * | 2006-01-11 | 2007-08-23 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| JP5042517B2 (ja) | 2006-04-10 | 2012-10-03 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2007311540A (ja) * | 2006-05-18 | 2007-11-29 | Renesas Technology Corp | 半導体装置の製造方法 |
| JP5309454B2 (ja) * | 2006-10-11 | 2013-10-09 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| JP5204964B2 (ja) * | 2006-10-17 | 2013-06-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2008192835A (ja) * | 2007-02-05 | 2008-08-21 | Tokyo Electron Ltd | 成膜方法,基板処理装置,および半導体装置 |
| JP2008311457A (ja) * | 2007-06-15 | 2008-12-25 | Renesas Technology Corp | 半導体装置の製造方法 |
| JP2009088421A (ja) | 2007-10-03 | 2009-04-23 | Renesas Technology Corp | 半導体装置の製造方法 |
-
2009
- 2009-03-05 JP JP2009051667A patent/JP5431752B2/ja not_active Expired - Fee Related
-
2010
- 2010-02-27 US US12/714,491 patent/US7964500B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2010206057A (ja) | 2010-09-16 |
| US20100227472A1 (en) | 2010-09-09 |
| US7964500B2 (en) | 2011-06-21 |
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