JP5413597B2 - 配線基板 - Google Patents

配線基板 Download PDF

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Publication number
JP5413597B2
JP5413597B2 JP2010043715A JP2010043715A JP5413597B2 JP 5413597 B2 JP5413597 B2 JP 5413597B2 JP 2010043715 A JP2010043715 A JP 2010043715A JP 2010043715 A JP2010043715 A JP 2010043715A JP 5413597 B2 JP5413597 B2 JP 5413597B2
Authority
JP
Japan
Prior art keywords
wiring
layer
terminal
terminal portion
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010043715A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011181642A (ja
JP2011181642A5 (https=
Inventor
道夫 堀内
純廣 市川
昌樹 真田
安衛 徳武
勇一 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010043715A priority Critical patent/JP5413597B2/ja
Publication of JP2011181642A publication Critical patent/JP2011181642A/ja
Publication of JP2011181642A5 publication Critical patent/JP2011181642A5/ja
Application granted granted Critical
Publication of JP5413597B2 publication Critical patent/JP5413597B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2010043715A 2010-03-01 2010-03-01 配線基板 Expired - Fee Related JP5413597B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010043715A JP5413597B2 (ja) 2010-03-01 2010-03-01 配線基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010043715A JP5413597B2 (ja) 2010-03-01 2010-03-01 配線基板

Publications (3)

Publication Number Publication Date
JP2011181642A JP2011181642A (ja) 2011-09-15
JP2011181642A5 JP2011181642A5 (https=) 2013-02-14
JP5413597B2 true JP5413597B2 (ja) 2014-02-12

Family

ID=44692866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010043715A Expired - Fee Related JP5413597B2 (ja) 2010-03-01 2010-03-01 配線基板

Country Status (1)

Country Link
JP (1) JP5413597B2 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5833398B2 (ja) 2011-06-27 2015-12-16 新光電気工業株式会社 配線基板及びその製造方法、半導体装置
JP6226779B2 (ja) 2014-03-10 2017-11-08 株式会社東芝 磁気メモリ、磁気メモリ装置、及び磁気メモリの動作方法
JP6220292B2 (ja) 2014-03-11 2017-10-25 株式会社東芝 磁気メモリ、磁気メモリの再生方法、および磁気メモリの記録方法
JP6193190B2 (ja) 2014-08-25 2017-09-06 株式会社東芝 磁気記憶素子および磁気メモリ
JP6523666B2 (ja) 2014-12-02 2019-06-05 東芝メモリ株式会社 磁気記憶素子および磁気メモリ
KR102689959B1 (ko) * 2019-03-12 2024-07-29 에스케이하이닉스 주식회사 인쇄 회로 기판을 포함하는 반도체 모듈

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002217240A (ja) * 2001-01-19 2002-08-02 Nec Tohoku Ltd フリップチップ実装構造及び配線方法
JP3872712B2 (ja) * 2002-04-18 2007-01-24 日本特殊陶業株式会社 多層配線基板
JP2004273480A (ja) * 2003-03-05 2004-09-30 Sony Corp 配線基板およびその製造方法および半導体装置

Also Published As

Publication number Publication date
JP2011181642A (ja) 2011-09-15

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