JP5412667B2 - 積層ｌｓｉチップのシステム検査のための方法および検査システム - Google Patents

積層ｌｓｉチップのシステム検査のための方法および検査システム Download PDF

Info

Publication number
JP5412667B2
JP5412667B2 JP2008333816A JP2008333816A JP5412667B2 JP 5412667 B2 JP5412667 B2 JP 5412667B2 JP 2008333816 A JP2008333816 A JP 2008333816A JP 2008333816 A JP2008333816 A JP 2008333816A JP 5412667 B2 JP5412667 B2 JP 5412667B2
Authority
JP
Japan
Prior art keywords
chip
lsi chip
inspection
lsi
probe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008333816A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010156569A5 (enExample
JP2010156569A (ja
Inventor
博 仲川
昌宏 青柳
義邦 岡田
祐教 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
National Institute of Advanced Industrial Science and Technology AIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute of Advanced Industrial Science and Technology AIST filed Critical National Institute of Advanced Industrial Science and Technology AIST
Priority to JP2008333816A priority Critical patent/JP5412667B2/ja
Publication of JP2010156569A publication Critical patent/JP2010156569A/ja
Publication of JP2010156569A5 publication Critical patent/JP2010156569A5/ja
Application granted granted Critical
Publication of JP5412667B2 publication Critical patent/JP5412667B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Measuring Leads Or Probes (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2008333816A 2008-12-26 2008-12-26 積層ｌｓｉチップのシステム検査のための方法および検査システム Expired - Fee Related JP5412667B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008333816A JP5412667B2 (ja) 2008-12-26 2008-12-26 積層ｌｓｉチップのシステム検査のための方法および検査システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008333816A JP5412667B2 (ja) 2008-12-26 2008-12-26 積層ｌｓｉチップのシステム検査のための方法および検査システム

Publications (3)

Publication Number Publication Date
JP2010156569A JP2010156569A (ja) 2010-07-15
JP2010156569A5 JP2010156569A5 (enExample) 2012-02-02
JP5412667B2 true JP5412667B2 (ja) 2014-02-12

Family

ID=42574595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008333816A Expired - Fee Related JP5412667B2 (ja) 2008-12-26 2008-12-26 積層ｌｓｉチップのシステム検査のための方法および検査システム

Country Status (1)

Country Link
JP (1) JP5412667B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8378701B2 (en) * 2010-09-30 2013-02-19 Texas Instruments Incorporated Non-contact determination of joint integrity between a TSV die and a package substrate
JP5509170B2 (ja) * 2011-09-29 2014-06-04 力成科技股▲分▼有限公司 マルチチップ積層体の製造方法
JP2013088288A (ja) * 2011-10-18 2013-05-13 Fujitsu Semiconductor Ltd 検査装置及び検査システム
TWI493203B (zh) * 2012-05-23 2015-07-21 Advantest Corp A test vehicle, a good judgment device, and a good judgment method
JP5967713B2 (ja) * 2012-12-13 2016-08-10 国立研究開発法人産業技術総合研究所 積層型ｌｓｉチップの絶縁膜の検査方法及び積層型ｌｓｉチップの製造方法
US10101365B2 (en) 2014-07-17 2018-10-16 Kabushiki Kaisha Nihon Micronics Semiconductor module, electrical connector, and inspection apparatus
JP6654096B2 (ja) * 2016-04-29 2020-02-26 日本電子材料株式会社 プローブカード
EP4314847A4 (en) * 2021-03-23 2025-03-05 Nielson Scientific, LLC CRYOGENIC PROBE CARD
KR102850097B1 (ko) * 2022-02-10 2025-08-26 삼성디스플레이 주식회사 발광 소자 테스트 장치

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6249239U (enExample) * 1985-09-13 1987-03-26
JPH07111995B2 (ja) * 1987-09-02 1995-11-29 東京エレクトロン株式会社 プローブ装置
JPH02103482A (ja) * 1988-10-13 1990-04-16 Matsushita Graphic Commun Syst Inc 集積回路装置
US5278961A (en) * 1990-02-22 1994-01-11 Hewlett-Packard Company Physical address to logical address translator for memory management units
JPH05275504A (ja) * 1992-01-16 1993-10-22 Toshiba Corp プローブカード
FR2700063B1 (fr) * 1992-12-31 1995-02-10 Sgs Thomson Microelectronics Procédé de test de puces de circuit intégré et dispositif intégré correspondant.
JPH1038924A (ja) * 1996-07-25 1998-02-13 Advantest Corp プローブカード
JP2001144149A (ja) * 1999-11-12 2001-05-25 Sony Corp 半導体測定冶具
US6718498B2 (en) * 2001-06-04 2004-04-06 Hewlett-Packard Development Company, L.P. Method and apparatus for the real time manipulation of a test vector to access the microprocessor state machine information using the integrated debug trigger

Also Published As

Publication number Publication date
JP2010156569A (ja) 2010-07-15

Similar Documents

Publication Publication Date Title
JP5412667B2 (ja) 積層ｌｓｉチップのシステム検査のための方法および検査システム
JP5914541B2 (ja) プローブカード
KR101341566B1 (ko) 소켓, 검사 장치, 그리고 적층형 반도체 소자 제조 방법
CN103063886B (zh) 用于探测集成电路的探针卡
EP2341356B1 (en) Method and device for measuring inter-chip signals
CN104465436B (zh) 衬底检查装置
CN107449948A (zh) 探针卡装置
CN103887193B (zh) 用于三维集成电路测试的装置
CN101154609B (zh) 凸块测试单元、装置及测试方法
US20110084720A1 (en) Test apparatus for electronic device package and method for testing electronic device package
JPH1048298A (ja) 半導体装置の高速試験方法
TWI359535B (en) Zif connectors and semiconductor testing device an
US11357106B2 (en) Memory system
CN103134961B (zh) 探针卡
TW202124974A (zh) 探針卡
JP4556023B2 (ja) システムインパッケージ試験検査装置および試験検査方法
CN115377066A (zh) 半导体装置和半导体器件
CN108562766A (zh) 芯片测试压接头及其探针机构
US20030234660A1 (en) Direct landing technology for wafer probe
JP4022698B2 (ja) 検査回路基板
KR102877155B1 (ko) 자동 시험 장치 및 그 인터페이스 장치
Chen et al. Fan-out wafer level chip scale package testing
JP4098976B2 (ja) マルチチップモジュール及びそのチップ間接続テスト方法
TWI754335B (zh) 檢測裝置
JP2003329726A (ja) 中継基板

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111121

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20111121

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20111122

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121105

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121121

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130118

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130927

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131023

R150 Certificate of patent or registration of utility model

Ref document number: 5412667

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees