JP5377275B2 - 情報処理装置又は情報処理方法 - Google Patents

情報処理装置又は情報処理方法 Download PDF

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Publication number
JP5377275B2
JP5377275B2 JP2009295617A JP2009295617A JP5377275B2 JP 5377275 B2 JP5377275 B2 JP 5377275B2 JP 2009295617 A JP2009295617 A JP 2009295617A JP 2009295617 A JP2009295617 A JP 2009295617A JP 5377275 B2 JP5377275 B2 JP 5377275B2
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JP
Japan
Prior art keywords
data
clock
external device
cycle
information processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009295617A
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English (en)
Japanese (ja)
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JP2011135531A (ja
JP2011135531A5 (https=
Inventor
昭好 桃井
浩一 森下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2009295617A priority Critical patent/JP5377275B2/ja
Priority to PCT/JP2010/007406 priority patent/WO2011077707A1/en
Priority to CN201080058944.4A priority patent/CN102668444B/zh
Priority to US13/518,344 priority patent/US8909970B2/en
Publication of JP2011135531A publication Critical patent/JP2011135531A/ja
Publication of JP2011135531A5 publication Critical patent/JP2011135531A5/ja
Application granted granted Critical
Publication of JP5377275B2 publication Critical patent/JP5377275B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
JP2009295617A 2009-12-25 2009-12-25 情報処理装置又は情報処理方法 Expired - Fee Related JP5377275B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009295617A JP5377275B2 (ja) 2009-12-25 2009-12-25 情報処理装置又は情報処理方法
PCT/JP2010/007406 WO2011077707A1 (en) 2009-12-25 2010-12-21 Information processing apparatus or information processing method
CN201080058944.4A CN102668444B (zh) 2009-12-25 2010-12-21 信息处理装置或信息处理方法
US13/518,344 US8909970B2 (en) 2009-12-25 2010-12-21 Information processing apparatus or information processing method which supplies a clock to an external device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009295617A JP5377275B2 (ja) 2009-12-25 2009-12-25 情報処理装置又は情報処理方法

Publications (3)

Publication Number Publication Date
JP2011135531A JP2011135531A (ja) 2011-07-07
JP2011135531A5 JP2011135531A5 (https=) 2013-02-14
JP5377275B2 true JP5377275B2 (ja) 2013-12-25

Family

ID=44195261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009295617A Expired - Fee Related JP5377275B2 (ja) 2009-12-25 2009-12-25 情報処理装置又は情報処理方法

Country Status (4)

Country Link
US (1) US8909970B2 (https=)
JP (1) JP5377275B2 (https=)
CN (1) CN102668444B (https=)
WO (1) WO2011077707A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8941430B2 (en) * 2012-09-12 2015-01-27 Nvidia Corporation Timing calibration for on-chip interconnect
CN116486878A (zh) * 2022-01-14 2023-07-25 晶豪科技股份有限公司 信号处理电路以及用以自校准tDQSCK的方法
US11916558B1 (en) * 2022-12-13 2024-02-27 Qualcomm Incorporated DDR phy parallel clock paths architecture

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59173839A (ja) * 1983-03-22 1984-10-02 Matsushita Electric Ind Co Ltd 直列デ−タ転送回路
JP3157029B2 (ja) 1992-02-28 2001-04-16 沖電気工業株式会社 データ受信装置
JP3367009B2 (ja) * 1995-08-31 2003-01-14 京セラ株式会社 プリンタ装置における同期式データ伝送方式
US5922076A (en) * 1997-09-16 1999-07-13 Analog Devices, Inc. Clocking scheme for digital signal processor system
JP3173457B2 (ja) 1998-03-23 2001-06-04 日本電気株式会社 データ通信装置
US6735709B1 (en) * 2000-11-09 2004-05-11 Micron Technology, Inc. Method of timing calibration using slower data rate pattern
JP2002247141A (ja) 2001-02-21 2002-08-30 Aisin Seiki Co Ltd シリアル通信装置
CN100412749C (zh) 2004-10-21 2008-08-20 威盛电子股份有限公司 存储器信号定时调校方法与相关装置
DE102005019041B4 (de) 2005-04-23 2009-04-16 Qimonda Ag Halbleiterspeicher und Verfahren zur Anpassung der Phasenbeziehung zwischen einem Taktsignal und Strobe-Signal bei der Übernahme von zu übertragenden Schreibdaten
CN101416437A (zh) 2006-04-05 2009-04-22 松下电器产业株式会社 可移动存储装置、相位同步方法、相位同步程序、其记录介质及主机终端
US8024599B2 (en) * 2007-03-08 2011-09-20 Sandisk Il Ltd Bias and random delay cancellation
KR100942953B1 (ko) * 2008-06-30 2010-02-17 주식회사 하이닉스반도체 데이터 전달 회로 및 그를 포함하는 반도체 메모리 장치
EP2351037A4 (en) * 2009-01-12 2011-12-28 Rambus Inc MESOCHRONIC SIGNALING SYSTEM WITH CORE ACTIVE SYNCHRONIZATION

Also Published As

Publication number Publication date
CN102668444A (zh) 2012-09-12
CN102668444B (zh) 2014-12-10
JP2011135531A (ja) 2011-07-07
WO2011077707A1 (en) 2011-06-30
US20120266009A1 (en) 2012-10-18
US8909970B2 (en) 2014-12-09

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