JP5369525B2 - PLL circuit and angular velocity sensor using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit which can accurately adjust a phase, and to an angular speed sensor that uses the circuit. <P>SOLUTION: The PLL circuit and the angular speed sensor using the same are constituted so that an AD converter 21 operates by a timing signal output from a voltage controlled oscillator 26, and a DA converter 24 outputs an analog signal, in response to the output value of the AD converter 21 on the timing signal output from a frequency divider 27. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention particularly relates to a PLL circuit used for attitude control of a moving body such as an aircraft and a vehicle, a navigation system, and the like, and an angular velocity sensor using the PLL circuit.

  Hereinafter, a conventional PLL circuit of this type will be described with reference to the drawings.

  FIG. 7 is a circuit diagram of a conventional PLL circuit.

  In FIG. 7, reference numeral 1 denotes a synchronization separation circuit. The synchronization separation circuit 1 extracts a synchronization signal from an externally input signal. Reference numeral 2 denotes a phase comparator. The phase comparator 2 changes the output voltage in a section where one input is L in accordance with the ratio of the other input. Reference numeral 3 denotes a low-pass filter, which removes a noise signal from the output signal of the phase comparator 2 and outputs an output signal. An amplifier 4 amplifies the output signal from the low-pass filter 3. Reference numeral 5 denotes a voltage controlled oscillator. The voltage controlled oscillator 5 varies the output frequency based on the voltage of the output signal from the amplifier 4. Reference numeral 6 denotes a frequency divider, which divides the output signal from the voltage controlled oscillator 5 by 1 / n.

  Next, the operation of the conventional PLL circuit configured as described above will be described.

  As illustrated in FIG. 8A, the synchronization separation circuit 1 outputs an output signal that is low for a certain time to the phase comparator 2.

  Then, as shown in FIGS. 8B and 8C, the phase comparator 2 has a period when the input signal a from the synchronization separation circuit 1 is low and the other input signal b is high. If the output voltage of the phase comparator 2 is lowered and the other input signal b is low, the output voltage of the phase comparator 2 is increased during that period.

  The signal c subjected to the level fluctuation by the input signal a and the other input signal b from the synchronous separation circuit 1 passes through the low pass filter 3 and the amplifier 4 to drive the voltage controlled oscillator 5. The voltage controlled oscillator 5 oscillates at a frequency n times that of the input signal, and the frequency divider 6 divides the frequency by 1 / n.

  Then, if an AD converter (not shown) is connected to the subsequent stage of the synchronization separation circuit 1 and a digital signal is input to the phase comparator 2, phase synchronization can be performed by a rectangular wave signal instead of an analog signal. It was possible.

As prior art document information relating to the invention of this application, for example, Patent Document 1 is known.
Japanese Patent Laid-Open No. 62-131630

  However, in the above-described conventional configuration, if the input signal to the phase comparator 2 is a digital signal, the period of one input of the phase comparator 2 is shortened due to the sampling interval of the digital signal, so that the level fluctuation is reduced. Since the output of the received signal c is reduced, the amount of fluctuation of the output frequency becomes unstable, which causes a problem that the phase cannot be adjusted accurately.

  SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object thereof is to provide a PLL circuit capable of accurately adjusting a phase and an angular velocity sensor using the PLL circuit.

  In order to achieve the above object, the present invention has the following configuration.

The invention described in claim 1 of the present invention includes an AD converter, a phase monitoring unit to which an output signal from the AD converter is input, a DA converter to which an output from the phase monitoring unit is input, A filter circuit that filters the output signal of the DA converter, a voltage controlled oscillator that outputs a signal of a different frequency according to the output signal from the filter circuit, and a frequency divider that divides the signal output from the voltage controlled oscillator The AD converter is operated by the timing signal output from the voltage controlled oscillator, and the output value of the AD converter at the timing signal output from the frequency divider is the median value. the intended output frequency of the voltage controlled oscillator and to output a direction of the analog signal which varies, according to this arrangement, the time delay due to the digital signal is generated, exactly And it has a effect that it is possible to adjust the phase.

According to a second aspect of the present invention, a sensor element having a drive electrode, a sense electrode, and a monitor electrode, an AD converter for AD-converting an output signal from the sensor element, and the AD converter A drive circuit comprising: an AGC circuit that sets the drive signal to a predetermined amplitude based on the output signal; and a drive means that applies a voltage to the drive electrode in the sensor element based on the output signal from the AGC circuit; A sense circuit that converts a signal output from a sense electrode in the sensor element into an angular velocity output signal, and a timing control circuit that outputs a timing signal to the sense circuit and the drive circuit, and the timing control circuit includes: an AD converter in the drive circuit, a phase monitoring means output signal from the AD converter is inputted, the output of the phase monitoring means A DA converter to be input, a filter circuit for filtering an output signal of the DA converter, a voltage controlled oscillator for inputting a rectangular wave having a different frequency according to the output signal from the filter circuit to the AD converter, The output signal from the voltage controlled oscillator is divided, and the divided output signal is constituted by a PLL circuit including a frequency dividing circuit for inputting to the DA converter, and the AD converter outputs the voltage controlled oscillator. An analog signal that operates in response to a timing signal and in which the frequency output from the voltage controlled oscillator changes so that the output value of the AD converter at the timing signal output from the frequency divider becomes the median value. which was to output, that according to this arrangement, even if the time delay due to the digital signal is generated, can be adjusted accurately phase It is those having an iodine effect.

As described above, the PLL circuit of the present invention includes an AD converter, a phase monitoring unit to which an output signal from the AD converter is input, a DA converter to which an output from the phase monitoring unit is input, A filter circuit for filtering the output signal of the DA converter, a voltage controlled oscillator for outputting a signal having a different frequency in accordance with the output signal from the filter circuit, and a frequency divider for dividing the signal output from the voltage controlled oscillator The AD converter is operated by the timing signal output from the voltage controlled oscillator, and the output value of the AD converter at the timing signal output from the frequency divider is the median value. in which the output frequency of the voltage controlled oscillator and to output a direction of the analog signal which varies, according to this arrangement, the time delay due to the digital signal is generated, exactly In which an excellent effect of being able to adjust the phase.

(Embodiment 1)
Hereinafter, the PLL circuit according to the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram of a PLL circuit according to Embodiment 1 of the present invention.

  In FIG. 1, reference numeral 21 denotes an AD converter, which converts an input analog signal into a digital signal. Reference numeral 22 denotes phase monitoring means. The phase monitoring means 22 receives a digital signal output from the AD converter 21, and the phase monitoring means 22 has a predetermined upper limit value according to the input value and its timing. Alternatively, either a lower limit value or an input value is output. Reference numeral 23 denotes a phase correction circuit. A signal output from the phase monitoring means 22 is input to the phase correction circuit 23. The phase correction circuit 23 outputs a value obtained by correcting the input signal by a predetermined value. is there. Reference numeral 24 denotes a DA converter. The DA converter 24 receives a signal output from the phase correction circuit 23, and the DA converter 24 outputs an analog signal corresponding to the input value. .

  Reference numeral 25 denotes a filter circuit composed of a loop filter. An analog signal output from the DA converter 24 is input to the filter circuit 25, and the filter circuit 25 performs filtering with a predetermined characteristic and outputs the filtered signal. Reference numeral 26 denotes a voltage controlled oscillator. The voltage controlled oscillator 26 receives a signal output from the filter circuit 25. The voltage controlled oscillator 26 receives a first timing signal having a different frequency according to the input analog value. Is output. Reference numeral 27 denotes a frequency divider. A signal output from the voltage controlled oscillator 26 is input to the frequency divider 27. The frequency divider 27 divides this signal by a predetermined value to generate a second timing signal. Is output. Thus, the AD converter 21 is operated by the first timing signal output from the voltage controlled oscillator 26, and the phase monitoring means 22 is operated by the second timing signal output from the frequency divider 27. It is a thing.

  Next, the operation of the PLL circuit according to Embodiment 1 of the present invention configured as described above will be described with reference to FIGS.

  When a sine wave analog signal is input to the AD converter 21, it is sampled at the timing of the first timing signal output from the voltage controlled oscillator 26 and converted to a digital value corresponding to the magnitude of the input analog signal. The digital value is input to the phase monitoring means 22. At this time, for example, it is converted into a positive / negative digital signal in which the median value of the sine wave signal is “0”. The phase monitoring means 22 outputs a digital value input at the timing of the second timing signal, and the digital value is input to the phase correction circuit 23 and corrected to a predetermined value, followed by DA conversion. Then, it is input to the converter 24, converted into an analog value corresponding to the digital value input by the DA converter 24, and output. The analog signal is input to the voltage controlled oscillator 26 through a filter circuit 25 formed of a loop filter, and a signal having a frequency corresponding to the input analog signal is output from the voltage controlled oscillator 26. This is an AD converter. This is fed back as a timing signal 21. At this time, the second timing signal is a synchronizing signal obtained by dividing the first timing signal, and the output value itself of the AD converter 21 at the timing of the second timing signal is the sine of the second timing signal. It becomes a value corresponding to the median value of the wave signal, that is, the phase shift amount from the zero point. That is, it has the same meaning as a value output from a phase comparator (not shown) in a normal PLL circuit. When the digital value output from the phase monitoring unit 22 is negative, an analog signal in a direction in which the frequency output from the voltage controlled oscillator 26 decreases, while when the digital value output from the phase monitoring unit 22 is positive. Outputs from the DA converter 24 an analog signal in a direction in which the frequency output from the voltage controlled oscillator 26 increases. The loop of the PLL circuit is controlled so that the analog signal output from the DA converter 24 is constant, that is, the digital value at the timing of the second timing signal is “0”. It will be. As a result, the sampling timing of the AD converter 21 is synchronized with the timing passing through the median value of the input analog signal, so that it is possible to accurately synchronize with the median value of the analog signal, that is, the zero point. It is.

  The phase monitoring means 22 monitors whether the input digital value exceeds a predetermined upper limit value and lower limit value. The value to be output is changed according to the timing at which the second timing signal is input. Specifically, the period from when the second timing signal is input until the input digital value falls below a predetermined upper limit value, then falls below a predetermined lower limit value, and further exceeds the lower limit value is phase 1 If the digital value input from the end of phase 1 exceeds the predetermined upper limit value is set as phase 2, and then the phase value is set to phase 3 until the next lower limit value is reached. When a timing signal is input, a signal having a predetermined lower limit value is output. When a second timing signal is input in phase 2, a digital value input at the timing of the second timing signal is output. When the second timing signal is input in phase 3, a signal having a predetermined upper limit value is output. A digital value output from the phase monitoring means 22 is input to the DA converter 24, and the DA converter 24 outputs an analog signal having a magnitude corresponding to the digital value. The signal is input to the filter circuit 25 formed of a loop filter, and after being filtered by the filter circuit 25, is input to the voltage controlled oscillator 26. In this manner, a frequency determined by a signal obtained by filtering an analog signal corresponding to the digital value output from the phase monitoring unit 22 is output from the voltage controlled oscillator 26. Since the phase monitoring means 22 sets the phase determination and the upper and lower limits of the output signal as described above, an analog signal within a certain range is input to the voltage controlled oscillator 26. As a result, the voltage The frequency of the signal output from the controlled oscillator 26 is limited. As a result, in the operation of the entire PLL circuit, a malfunction other than a frequency obtained by multiplying the frequency of the input analog signal by the frequency division value in the frequency divider, such as a so-called double frequency lock, is prevented, and the PLL circuit is predetermined. It can be locked at a frequency of.

  Further, in the phase correction circuit 23 to which the signal output from the phase monitoring means 22 is input, the input phase comparison value is increased / decreased by a predetermined value to output the phase to be locked with the resolution of the digital value. It is possible to make fine adjustments by the minute. For example, if the phase correction circuit 23 adds and outputs a positive value, the voltage-controlled oscillator 26 outputs a frequency that is increased by the amount added compared to the case where the value is not added. It will lock to an earlier point.

  Further, in the AD converter 21, when a predetermined number of clocks are delayed and output by AD conversion or calculation, etc., the AD converter 21 locks with a phase shifted by the delay, but the output of the phase monitoring means 22 The timing at which the second timing signal passes through the median value of the input analog signal is obtained by outputting the value at a timing shifted by the number of clocks corresponding to the delay from the timing of the second timing signal. This makes it possible to accurately synchronize with the median value of the analog signal, that is, the zero point.

(Embodiment 2)
Hereinafter, an angular velocity sensor using a PLL circuit according to Embodiment 2 of the present invention will be described with reference to the drawings.

  FIG. 4 is a circuit diagram of an angular velocity sensor using a PLL circuit according to Embodiment 2 of the present invention.

  In FIG. 4, reference numeral 30 denotes a sensor element. The sensor element 30 includes a vibrating body 31, a driving electrode 32 having a piezoelectric body for vibrating the vibrating body 31, and a piezoelectric body that generates an electric charge according to the vibration state. And a pair of sense electrodes having a piezoelectric body that generates an electric charge when an angular velocity is applied to the sensor element 30. Further, the pair of sense electrodes in the sensor element 30 includes a first sense electrode 34 and a second sense electrode 35 that generates charges having a polarity opposite to that of the first sense electrode 34. Reference numeral 41 denotes a drive circuit. The drive circuit 41 includes an input switching unit 42, a DA conversion unit 43, an integration unit 44, a comparison unit 45, a filter circuit 46 including a digital filter, an AGC circuit 47, and a drive circuit 48. Yes. The input switching means 42 in the drive circuit 41 is connected to the monitor electrode 33 in the vibrating body 31 and is constituted by an analog switch that operates at the second timing Φ2. Further, the DA switching means 49 in the drive circuit 41 has a first reference voltage 50 and a second reference voltage 51, and the first reference voltage 50 and the second reference voltage 51 are set to the second reference voltage 50. Switching is performed by a predetermined signal at timing Φ2. Further, the drive circuit 41 is provided with a DA output means 52. The DA output means 52 is connected to a capacitor 53 to which an output signal of the DA switching means 49 is input, to both ends of the capacitor 53, and It is composed of SWs 54 and 55 that operate at the first timing Φ1 and discharge the electric charge of the capacitor 53. The DA switching means 49 and the DA output means 52 constitute a DA converting means 43. The DA converting means 43 discharges the capacitor 53 at the first timing Φ1, and further the second timing. Charges corresponding to the reference voltage output by the DA switching means 49 at Φ2 are input / output. Reference numeral 56 denotes a switch, and the outputs of the input switching means 42 and the DA conversion means 43 are input to the SW 56, and the SW 56 is output at the second timing Φ2.

  Reference numeral 44 denotes an integrating means, to which the output of the SW 56 is input. The integrating means 44 comprises an operational amplifier 57 and a capacitor 58 connected to the feedback of the operational amplifier 57. Then, it operates at the second timing Φ2, and the input signal to the integrating means 44 is integrated by the capacitor 58. Reference numeral 45 denotes a comparison means. The comparison means 45 receives an integration signal output from the integration means 44. The comparison means 45 compares the integration signal with a predetermined value, and compares the comparison signal. And a D-type flip-flop 60 to which a 1-bit digital signal output from the device 59 is input. The D-type flip-flop 60 latches the 1-bit digital signal and outputs a latch signal at the start of the first timing Φ1, and this latch signal is the DA switching means of the DA conversion means 43. 49, the first reference voltage 50 and the second reference voltage 51 are switched. The input switching means 42, DA converting means 43, integrating means 44, and comparing means 45 constitute an AD converter 61 composed of a ΣΔ modulator.

  Further, the pulse density modulation symbol output from the AD converter 61 is input to the filter circuit 46, and a signal of the resonance frequency of the vibrating body 31 is extracted and a multi-bit signal from which noise components are removed is output. Then, this multi-bit signal is input to a half-wave rectification filter circuit (not shown) provided in the AGC circuit 47 to be converted into an amplitude information signal. When the amplitude information signal is large, the AGC circuit 47 attenuates the output multi-bit signal of the filter circuit 46, whereas when the amplitude information signal is small, the AGC circuit 47 outputs the output multi-bit signal of the filter circuit 46. A signal obtained by amplifying the bit signal is input to the drive circuit 48 and adjusted so that the vibration of the vibrating body 31 has a constant amplitude.

  The drive circuit 48 includes a digital value output means 62 that holds two values, an addition / integration calculation means 63 that adds and integrates the output signal from the AGC circuit 47 and the output of the digital value output means 62, and this addition A value comparison means 65 for comparing the output from the integral calculation means 63 with a comparison constant value 64; a value switching means 66 for switching the digital value output from the digital value output means 62 in accordance with the output from the value comparison means 65; It has a digital ΣΔ modulator 68 composed of a flip-flop 67 that latches the output of the value comparing means 65 at a predetermined timing. The multi-bit signal output from the AGC circuit 47 by the digital ΣΔ modulator 68 is modulated and output as a 1-bit pulse density modulation signal, and this pulse density modulation signal is input to the analog filter 69, and further the sensor element 30. The frequency component harmful to driving the signal is filtered and output to the sensor element 30.

  Reference numeral 71 denotes a timing control circuit. The timing control circuit 71 inputs a multi-bit signal output from the filter circuit 46 in the drive circuit 41, generates a timing signal of the first timing Φ1 and the second timing Φ2, and drives it. The timing signal of the third timing Φ3, the fourth timing Φ4, the fifth timing Φ5, and the sixth timing Φ6 is output to the circuit 41, and to the sense circuit 81.

  The internal configuration of the timing control circuit 71 will be described later.

  The sense circuit 81 includes an AD converter 82 composed of a ΣΔ modulator and an arithmetic means 83. 84 is an input switching means, and this input switching means 84 is connected to the first sense electrode 34 in the sensor element 30 and is operated at the fourth timing Φ4. The analog switch 86 is connected to the sense electrode 35 and operates at the sixth timing Φ6. With this configuration, the input switching unit 84 switches and outputs the input signal from the first sense electrode 34 or the second sense electrode 35 at the fourth timing Φ4 or the sixth timing Φ6. Reference numeral 87 denotes DA switching means. This DA switching means 87 has a first reference voltage 88 and a second reference voltage 89, and the first reference voltage 88 and the second reference voltage 89 are set to a predetermined signal. Is switched by. Reference numeral 90 denotes DA output means. The DA output means 90 is connected to the capacitor 91 to which the output signal of the DA switching means 87 is input, and is connected to both ends of the capacitor 91, and the third timing Φ3 and the fifth timing. It is composed of SWs 92 and 93 that operate at Φ5 and discharge the electric charge of the capacitor 91. The DA switching means 87 and the DA output means 90 constitute a DA converting means 94, and the DA converting means 94 discharges the electric charge of the capacitor 91 at the third timing Φ3 and the fifth timing Φ5, Furthermore, charges corresponding to the reference voltage output by the DA switching means 87 are input and output at the fourth timing Φ4 and the sixth timing Φ6.

  Reference numeral 95 denotes an SW. The outputs of the input switching means 84 and the DA conversion means 94 are input to the SW 95 and output at the fourth timing Φ4 and the sixth timing Φ6. Reference numeral 96 denotes an integrating circuit, to which the output of the SW 95 is input. The integrating circuit 96 is connected to an operational amplifier 97 and a pair of feedback connected to the operational amplifier 97 in parallel. The capacitors 98 and 99 and a pair of SWs 100 and 101 connected to the capacitors 98 and 99 are included. Further, the SW 100 operates at the third timing Φ3 and the fourth timing Φ4, and the input signal to the integration circuit 96 is integrated into the capacitor 98 and the integrated value is held. Further, the SW 101 operates at the fifth timing Φ5 and the sixth timing Φ6, and the input signal to the integrating circuit 96 is integrated into the capacitor 99 and the integrated value is held. The integrating means 102 is constituted by the SW 95 and the integrating circuit 96.

  Reference numeral 103 denotes a comparison means. The comparison means 103 receives the integration signal output from the integration means 102. The comparison means 103 compares the integration signal with a predetermined value, and compares the comparison signal. And a D-type flip-flop 105 to which a 1-bit digital signal output from the device 104 is input. The D-type flip-flop 105 latches the 1-bit digital signal and outputs a latch signal at the start of the fourth timing Φ4 and the sixth timing Φ6. The reference voltage 88, 89 is input to the DA switching means 87 of the means 94. The input switching means 84, DA conversion means 94, integration means 102 and comparison means 103 constitute an AD converter 82.

  In addition, the AD converter 82 has the above-described configuration, and ΣΔ modulates the electric charges output from the first sense electrode 34 and the second sense electrode 35 in the sensor element 30 and converts them into a 1-bit digital signal for output. It is.

  A latch circuit 106 receives a 1-bit digital signal output from the comparator 104 in the comparing means 103 of the AD converter 82 and latches the 1-bit digital signal. The flip-flops 107 and 108 are used. The D-type flip-flop 107 latches the 1-bit digital signal at the fourth timing Φ4, and the D-type flip-flop 108 latches the 1-bit digital signal at the sixth timing Φ6. Reference numeral 109 denotes a difference calculation means. The difference calculation means 109 receives a pair of 1-bit digital signals latched and output by the pair of D-type flip-flops 107 and 108 in the latch circuit 106, and the pair of 1-bit digital signals. A 1-bit difference operation for calculating a signal difference is realized by a replacement process. That is, when the pair of 1-bit digital signals input to the difference calculation means 109 are “00”, “01”, “10”, and “11”, they are replaced with “0”, “−1”, “1”, and “0”, respectively. Output. Reference numeral 110 denotes a correction calculation means. The correction calculation means 110 receives a 1-bit difference signal output from the difference calculation means 109, and realizes a correction calculation between the 1-bit difference signal and predetermined correction information by replacement processing. That is, as described above, when the 1-bit difference signal input to the correction calculation means 110 is “0”, “1”, “−1”, and the correction information is “5”, for example, The output is replaced with “0”, “5”, and “−5”. Reference numeral 111 denotes a filter circuit composed of a digital filter. The digital differential signal output from the correction calculation unit 110 is input to the filter circuit 111 to perform a filtering process for removing noise components. The latch circuit 106, the difference calculation means 109, the correction calculation means 110, and the filter circuit 111 constitute a calculation means 83. The arithmetic means 83 latches a pair of 1-bit digital signals at the fourth and sixth timings, performs a difference operation, a correction operation, and a filtering process, and outputs a multi-bit signal.

  The timing control circuit 71 includes a PLL circuit 121, timing generation circuits 122 and 123, and an amplitude determination circuit 124.

  The PLL circuit 121 multiplies the frequency of the multi-bit signal output from the filter circuit 46 in the drive circuit 41, integrates and reduces the phase noise in time, and outputs a signal to the timing generation circuits 122 and 123. It is. The phase monitoring means 126 receives a rectangular wave signal obtained by shaping the multi-bit signal output from the filter circuit 46 and an output signal from the frequency divider 126a. The second timing signal by the frequency divider 126a is a synchronization signal obtained by dividing the first timing signal by the voltage controlled oscillator 129, which will be described later, and is a drive that is an AD converter at the timing of the second timing signal. The output value itself of the circuit 41 is a value corresponding to the median value of the sine wave signal of the second timing signal, that is, the phase shift amount from the zero point. The signal output from the phase monitoring means 126 is input to the filter circuit 127 formed of a loop filter via the phase correction circuit 126b, and this filter circuit 127 converts the signal into a DC signal with a small AC component. The output signal and the constant voltage value are input to the timing switching means 128. One of the timing switching means 128 is connected to the filter circuit 127 as described above, and the other is electrically connected to the constant voltage output device.

  The multi-bit signal output from the filter circuit 46 is input to the amplitude determination circuit 124. The amplitude determination circuit 124 monitors the amplitude information of the multi-bit signal output from the filter circuit 46. If the amplitude information is greater than or equal to the target amplitude, the timing switching means 128 outputs the output of the filter circuit 127. On the other hand, when the amplitude information of the multi-bit signal output from the filter circuit 46 is equal to or less than the target amplitude, the timing switching unit 128 switches so as to select a constant voltage value.

  The output voltage of the timing switching means 128 is input to the voltage controlled oscillator 129. The voltage controlled oscillator 129 is a variable frequency oscillator that oscillates a frequency signal corresponding to an input voltage. The oscillation signal output from the voltage controlled oscillator 129 is input to the frequency divider 126 a and the timing generation circuits 122 and 123. The

  The timing generation circuit 122 generates a timing signal having a first timing Φ1 and a second timing Φ2 based on a signal output from the PLL circuit 121, and outputs the timing signal to the drive circuit 41. The generation circuit 123 divides the two periods of the monitor signal into a third timing Φ 3, a fourth timing Φ 4, a fifth timing Φ 5, and a sixth timing Φ 6, generates this timing signal, and outputs it to the sense circuit 81. To do.

  Next, the operation of the angular velocity sensor using the PLL circuit according to the second embodiment of the present invention configured as described above will be described.

  When a drive signal is applied to the drive electrode 32 of the sensor element 30, the vibrating body 31 resonates and charges are generated at the monitor electrode 33. The charges generated on the monitor electrode 33 are input to the AD converter 61 in the drive circuit 41 and converted into a pulse density modulation signal. The pulse density modulation signal is input to the filter circuit 46, where the resonance frequency of the vibrating body 31 is extracted and a multi-bit signal from which noise components have been removed is output.

  The operation of the AD converter 61 in this case will be described below. The AD converter 61 operates by repeating the first timing Φ1 and the second timing Φ2 that are synchronized with the monitor signal output from the timing control circuit 71. At the first timing Φ1, the sensor element is operated. The signal output from the monitor electrode 33 at 30 is ΣΔ modulated and converted into a 1-bit digital signal.

  The operation at the above two timings will be described one by one. First, at the first timing Φ1, the 1-bit digital signal output from the comparator 59 is input to the comparator 59 of the comparator 45 that compares the integrated value held in the capacitor 58 in the integrator 44. At the rising edge of the first timing Φ 1, the signal is latched by the D-type flip-flop 60, and this latch signal is input to the DA switching means 49 of the DA conversion means 43. Further, SW 54 and SW 55 in the DA output means 52 are turned on, and the electric charge held in the capacitor 53 is discharged.

  Next, at the second timing Φ2, the first reference voltage 50 and the second reference voltage 51 are switched and input to the capacitor 53 in accordance with the latch signal input to the DA switching means 49, and the DA conversion means. The electric charge according to the reference voltage switched from 43 is output. Further, the input switching means 42 is turned on, and the charge generated from the monitor electrode 33 of the sensor element 30 is input. Further, the SW 56 in the integrating unit 44 is turned on, and the charges output from the input switching unit 42 and the DA converting unit 43 are input to the integrating unit 44. Accordingly, at the second timing Φ2, the sum of the charge amount indicated by the hatched portion in FIG. 5A and the charge amount output from the DA conversion unit 43 is integrated and held in the capacitor 58 in the integration unit 44. It will be.

  Due to the above operation at the first timing Φ1 and the second timing Φ2, the charge amount corresponding to the amplitude value output from the monitor electrode 33 of the sensor element 30 is ΣΔ-modulated, and the signal at the first timing Φ1 is At the time of rising, it is output as a 1-bit digital signal.

  With the above operation, the charge amount output from the monitor electrode 33 in the sensor element 30 is ΣΔ modulated by the AD converter 61 and output as a 1-bit digital signal at the above timing.

  Further, the multi-bit signal shown in FIG. 5B outputted from the filter circuit 46 in the drive circuit 41 is inputted to a half-wave rectification filter circuit (not shown) provided in the AGC circuit 47, whereby amplitude information is obtained. Convert to signal. The AGC circuit 47 attenuates the output multi-bit signal of the filter circuit 46 when the amplitude information signal is large, while the output of the filter circuit 46 when the amplitude information signal is small. A signal obtained by amplifying the multi-bit signal is input to the drive circuit 48 and adjusted so that the vibration of the vibrating body 31 has a constant amplitude.

  The addition / integration calculation means 63 of the digital ΣΔ modulator 68 has a multi-bit signal output from the AGC circuit 47 and a value for holding one of the two values and outputting one of the values of the digital value output means 62. A constant value output from the switching means 66 is input, added and integrated. The integration value output from the addition / calculation operation means 63 is compared with the comparison constant value 64 by the value comparison means 65, and the comparison result is output. The comparison result is latched and output at a predetermined timing by the flip-flop 67. The constant value output from the value switching means 66 is switched by the output of the flip-flop 67. At this time, when the output value of the addition / integration calculating means 63 is smaller than the comparison constant value 64, the larger value of the two values of the digital value output means 62 is selected, and in the opposite case, the smaller value is selected. And operate to be output. By repeating this operation, the multi-bit signal output from the AGC circuit 47 is modulated from the flip-flop 67 into a 1-bit pulse density modulation signal and output. Here, when the signal input to the digital ΣΔ modulator 68 is, for example, 10 bits (= ± 9 bits), the comparison constant value 64 is “0”, and the binary value of the digital value output means 62 is “511” “−511”. "It is desirable to set it above.

  Note that in ΣΔ modulation, oversampling is performed, and the quantization noise is noise-shaped in a high frequency range. Therefore, the noise component of a high frequency component is included, but the response of the sensor element 30 cannot respond to such a high frequency, so the pulse density It vibrates not at the sampling frequency of the modulation signal but at a predetermined oversampled frequency component. If the sensor element 30 has a high response gain at a high frequency and noise of such a high frequency component becomes a problem, the problematic frequency component of the output signal of the digital ΣΔ modulator 68 is reduced. By adding the set analog filter 69, it is possible to realize the drive circuit 41 with lower noise and higher accuracy.

  Further, when the sensor element 30 is bent and vibrated at a speed V in the driving direction shown in FIG. 4, when the sensor element 30 rotates at an angular speed ω around the central axis in the longitudinal direction of the vibrating body 31, A Coriolis force of F = 2 mV × ω is generated in the sensor element 30. Due to this Coriolis force, electric charges are generated in the pair of sense electrodes 34 and 35 of the sensor element 30 as shown in FIGS. 6 (a) and 6 (b). Since the charges generated in the sense electrodes 34 and 35 are generated by Coriolis force, the phase is advanced by 90 degrees from the signal generated in the monitor electrode 33. The output signals generated at the pair of sense electrodes 34 and 35 are in a relationship between a positive polarity signal and a negative polarity signal as shown in FIGS. 6 (a) and 6 (b).

  The operation of the AD converter 82 in this case will be described below. The AD converter 82 operates by repeating the third timing Φ3, the fourth timing Φ4, the fifth timing Φ5, and the sixth timing Φ6. At the third timing Φ3 and the fourth timing Φ4, The positive polarity signal output from the sense electrode 34 in the sensor element 30 is ΣΔ modulated and converted into a 1-bit digital signal, and the negative polarity signal is ΣΔ modulated and converted to 1 bit at the fifth timing Φ5 and the sixth timing Φ6. Converted to a digital signal.

  The operation at the above four timings will be described one by one. First, at the third timing Φ 3, the SW 100 connected to the capacitor 98 in the integrating means 102 is turned ON, and the integrated value held in the capacitor 98 is input to the comparator 104 in the comparing means 103 and the comparison result is 1 It is output as a bit digital signal. Further, the SWs 92 and 93 in the DA conversion means 94 are turned on, and the electric charge held in the capacitor 91 is discharged.

  Next, at the fourth timing Φ4, the 1-bit digital signal output from the comparator 104 of the comparator 103 is latched in the D-type flip-flop 105 at the rise of the fourth timing Φ4, and this latch signal is converted to the DA converter. Input to the DA switching means 87 of the means 94. In accordance with the input latch signal, the reference voltages 88 and 89 are switched and input to the capacitor 91, and charges corresponding to the switched reference voltage are output from the DA converter 94. At the same time, the switch 85 is turned on in the input switching means 84, and the electric charge generated from the first sense electrode 34 of the sensor element 30 is output. Further, the SW 95 in the integrating means 102 is turned on, and the charges output from the input switching means 84 and the DA converting means 94 are input to the integrating circuit 96. As a result, at the fourth timing Φ4, the capacitor 98 in the integration circuit 96 integrates and holds the sum of the charge amount indicated by the hatched portion in FIG. 6A and the charge amount output from the DA conversion means 94. It will be.

  As a result of the above operations at the third timing Φ3 and the fourth timing Φ4, the charge amount corresponding to half of the amplitude value output from the first sense electrode 34 of the sensor element 30 is ΣΔ modulated. .

  Similarly to the operation at the third timing Φ3 and the fourth timing Φ4, at the fifth timing Φ5 and the sixth timing Φ6, the amplitude value output from the second sense electrode 35 of the sensor element 30 is changed. The amount of charge corresponding to half is ΣΔ modulated.

  With the above operation, the amount of charge corresponding to half of the amplitude width of the charge output from the pair of sense electrodes 34 and 35 in the sensor element 30 is ΣΔ modulated by one AD converter 82 to form a pair of 1-bit digital signals. It is output at the above timing.

  In addition, the charges output from the pair of sense electrodes 34 and 35 in the sensor element 30 are not only the sense signal which is generated by the Coriolis force due to the angular velocity and whose phase is advanced by 90 degrees from the signal generated in the monitor electrode 33, but also the monitor signal. Since there is an unnecessary signal in phase with the signal, a case where a combined signal of the sense signal and the unnecessary signal is output from the pair of sense electrodes 34 and 35 in the sensor element 30 will be described. The sense signal generated by the Coriolis force due to the angular velocity is shown in FIGS. 6 (a) and 6 (b), and as described above, at the fourth timing Φ4 and the sixth timing Φ6, the integrating circuit 96 causes the sense signal to be as shown in FIG. a) The charge amount indicated by the shaded portion in (b), that is, the charge amount corresponding to half of the amplitude value is integrated. Further, unnecessary signals generated from the sense electrodes 34 and 35 are shown in FIGS. 6C and 6D, and, similar to the sense signal, at the fourth timing Φ4 and the sixth timing Φ6, FIG. The amount of charge indicated by the hatched portion in (d), that is, the amount of charge in the interval from the maximum value to the minimum value of the amplitude of the unnecessary signal is integrated, and this is canceled when integrated based on the median value of the amplitude. Thus, the charge amount becomes “0”. That is, a so-called synchronous detection process in which the unnecessary signal is canceled and the charge amount according to the amplitude of the sense signal is integrated by the operation of the integrating means 102 at the fourth timing Φ4 and the sixth timing Φ6 is a pair of inputs. Will be implemented for each of the signals. Therefore, similarly to the description of the operation when there is no unnecessary signal, the AD converter 82 ΣΔ modulates the signal subjected to the synchronous detection processing, converts it to a 1-bit digital signal, and outputs it.

  With the above operation, the pair of output signals in the sensor element 30 can be subjected to ΣΔ modulation while performing synchronous detection processing, and the digital value of the signal subjected to such synchronous detection is converted into a normal IV conversion circuit, phase The circuit can be obtained without the need for an analog circuit such as a detector and a synchronous detection circuit, and with a circuit scale much smaller than when these are used, that is, with a small size and low cost.

  Next, the operation of the calculation means 83 will be described. First, the 1-bit digital signal output from the comparator 104 in the comparator 103 of the AD converter 82 is latched in the D-type flip-flop 107 of the latch circuit 106 at the fourth timing Φ4. At the sixth timing Φ 6, the 1-bit digital signal output from the comparator 104 in the comparison unit 103 of the AD converter 82 is latched in the D-type flip-flop 108 of the latch circuit 106.

  As described above, the pair of 1-bit digital signals latched by the pair of D-type flip-flops 107 and 108 exclude unnecessary signals output from the pair of sense electrodes 34 and 35 in the sensor element 30. The charge amount corresponding to half of the amplitude value is converted into a digital value by ΣΔ modulation. Next, a pair of 1-bit digital signals output from the latch circuit 106 are input to a 1-bit difference calculation means 109, and a difference between the pair of 1-bit digital signals is calculated to output a 1-bit difference signal. Here, the 1-bit difference signal at the third timing Φ3 is the difference between the 1-bit digital signals latched at the fourth timing Φ4 and the sixth timing Φ6 in the previous synchronization, and this 1-bit difference signal. The signal is a symbol representing an amplitude value excluding unnecessary signals of signals output from the pair of sense electrodes 34 and 35 in the sensor element 30 shown in FIGS. As a result of the above operation, the pair of input signals in the relationship between the positive polarity signal and the negative polarity signal output from the pair of sense electrodes 34 and 35 in the sensor element 30 are integrated using the same single integration means 102. The influence on the relative error of the integration result of the pair of input signals due to the characteristics of the individual integration circuits is greatly reduced as compared with the case where the integration is performed separately by the two integration circuits. Similarly, the DA conversion means 94 is configured to use the same one DA conversion means for signal processing of a pair of input signals. Further, by comparing the pair of integration results with the same reference voltage and the comparator in the comparison means 103, the influence on the relative error of the comparison result of the characteristics of the comparator and the fluctuation of the reference voltage is greatly reduced. As described above, since a pair of input signals are subjected to signal processing using the same integration circuit 96, DA conversion means 94, and comparison means 103, compared to the case where signal processing is performed using a plurality of each means. The influence of the relative error of each means is greatly reduced.

  In addition, since the influence of the reference voltage fluctuation in each means due to the influence of the power supply voltage change and the temperature change is similarly applied to the pair of input signals, the pair of input signals is obtained by the 1-bit difference calculation means 109 included in the calculation means 83. By calculating the difference between the signal processing results, it is possible to cancel the influence of the reference voltage fluctuation or the like in each means, thereby obtaining the effect that the difference between the pair of input signals can be AD converted with high accuracy.

  At the same time, the influence of in-phase noise components and offset components including a pair of input signals output from the pair of sense electrodes 34 and 35 in the sensor element 30 and input to the AD converter 82 can be canceled. Thus, an effect that a difference signal between a pair of input signals can be formed with high accuracy is obtained.

  Further, the 1-bit difference calculation that takes the difference between a pair of input signals is a pair of comparison signals input to the difference calculation means 109 when the output signal of the comparison means 103 is a 1-bit signal consisting of “1” and “0”. Is limited to the four types “00”, “01”, “10”, and “11”, and the result of taking the difference is also determined as “0”, “−1”, “1”, and “0”. This is a 1-bit digital operation that can obtain a result of performing a subtraction process according to an input signal with a very simple circuit configuration. In this way, by setting the pair of input signals subjected to the subtraction processing as one difference signal, and performing signal processing such as low-pass and decimation by the filter circuit 111 formed of a digital filter, the pair of input signals is Compared to the case where a digital filter that performs signal processing by low-pass or decimation is prepared for each input signal, and differential calculation processing is performed using an arithmetic unit that can add and subtract multi-bits after multi-biting by a filter circuit consisting of digital filters. Thus, there is an effect that the arithmetic circuit such as the difference calculating means 109 and the filter circuit 111 including a digital filter can be configured with a very small circuit scale, that is, with a small size and a low cost, and high-accuracy signal processing can be realized. It is what

  Next, a 1-bit difference signal output from the 1-bit difference calculation unit 109 is input to the correction calculation unit 110, and a correction calculation between the 1-bit difference signal and predetermined correction information is performed by a replacement process. As described above, this correction calculation uses the fact that the 1-bit difference signal is limited to the three values “0”, “1”, and “−1”, for example, when the predetermined correction information is “5”. The 1-bit differential signal “0”, “1”, “−1” input to the correction calculation means is replaced with “0”, “5”, “−5”, respectively, so that multiplication is realized to correct the signal. It is possible.

  The multibit signal output from the filter circuit 46 is input to the amplitude determination circuit 124 in the timing control circuit 71 and the phase monitoring means 126 as a waveform-shaped rectangular wave signal. The amplitude determination circuit 124 monitors the amplitude information of the multi-bit signal output from the filter circuit 46. When the amplitude information is 50% or more of the target amplitude, the timing switching means 128 is formed of a loop filter. It switches so that the output signal of the filter circuit 127 may be selected. At this time, the PLL circuit 121 becomes a closed loop, which multiplies the monitor signal of the tuning fork drive frequency as an input signal and outputs a signal obtained by integrating and reducing the phase noise in time, so that a signal synchronized with the inherent drive frequency of the sensor element 30 is generated. It is input to the timing generation circuits 122 and 123.

  On the other hand, when the amplitude information of the multi-bit signal output from the filter circuit 46 is 50% or less of the target amplitude, the timing switching means 128 switches to select a constant voltage value, and the voltage controlled oscillator 129 outputs a constant voltage. A signal having a fixed frequency corresponding to the voltage value is output, and this signal is input to the timing generation circuits 122 and 123.

  Based on the signal output from the PLL circuit 121 under the above conditions, the timing generation circuit 122 switches the input switching means 42, DA switching means 49, SW54, SW55, SW56 and D-type flip-flop 60 in the drive circuit 41. Timing signals of the first timing Φ1 and the second timing Φ2 as shown in FIG. 5C which are timings are generated and output. In addition, the timing generation circuit 123 includes a third timing Φ 3 and a fourth timing that are switching timings of the input switching unit 84, the DA switching unit 87, SW 92, SW 93, SW 95, SW 100, SW 101 and the D-type flip-flop 105 in the sense circuit 81. Are generated and output at timing Φ4, fifth timing Φ5, and sixth timing Φ6.

  The PLL circuit according to the present invention has an effect that the phase can be accurately adjusted even when a time delay due to a digital signal occurs. In particular, the attitude control and navigation system of a moving body such as an aircraft or a vehicle. It becomes useful by applying to the above.

Circuit diagram of PLL circuit in Embodiment 1 of the present invention The figure which shows the state which the same PLL circuit operate | moves The figure which shows the state which the same PLL circuit operate | moves Circuit diagram of angular velocity sensor using PLL circuit in Embodiment 2 of the present invention (A)-(c) The figure which shows the operation state of the same angular velocity sensor (A)-(d) The figure which shows the operation state of the same angular velocity sensor Circuit diagram of conventional PLL circuit (A)-(c) The circuit diagram which shows the operation state of the conventional PLL circuit

DESCRIPTION OF SYMBOLS 21 AD converter 22 Phase monitoring means 23 Phase correction circuit 24 DA converter 25 Filter circuit 26 Voltage control oscillator 27 Frequency divider 30 Sensor element 32 Drive electrode 33 Monitor electrode 34, 35 Sense electrode 41 Drive circuit 46 Filter circuit 47 AGC circuit 61, 82 AD converter 71 Timing control circuit 81 Sense circuit 94 DA conversion means 121 PLL circuit 129 Voltage controlled oscillator

Claims (2)

AD converter, phase monitoring means to which an output signal from the AD converter is input, a DA converter to which an output from the phase monitoring means is input, and a filter circuit for filtering the output signal of the DA converter A voltage-controlled oscillator that outputs a signal having a different frequency according to an output signal from the filter circuit, and a frequency divider that divides the signal output from the voltage-controlled oscillator, and the AD converter controls the voltage. A direction in which the frequency output from the voltage controlled oscillator changes so that the DA converter operates at the timing signal output from the oscillator and the output value of the AD converter at the timing signal output from the frequency divider becomes the median value. PLL circuit configured to output an analog signal. A sensor element having a drive electrode, a sense electrode, and a monitor electrode, an AD converter for AD converting an output signal from the sensor element, and a drive signal based on the output signal from the AD converter A signal output from a sense circuit in the sensor element, and a drive circuit comprising an AGC circuit set to amplitude and a drive means for applying a voltage to the drive electrode in the sensor element based on an output signal from the AGC circuit And a timing control circuit that outputs a timing signal to the sense circuit and the drive circuit, and the timing control circuit includes an AD converter in the drive circuit, and the AD converter. phase monitoring means output signal from is inputted, a DA converter output from the phase monitor unit is input, the DA A filter circuit for filtering the output signal of the converter, a voltage controlled oscillator for inputting a rectangular wave having a different frequency according to the output signal from the filter circuit to the AD converter, and an output signal from the voltage controlled oscillator. And a frequency dividing circuit for inputting the frequency-divided output signal to the DA converter, and the AD converter is operated by a timing signal output from the voltage controlled oscillator, and the DA converter An angular velocity sensor configured to output an analog signal in a direction in which the frequency output from the voltage controlled oscillator changes so that the output value of the AD converter at the timing signal output from the frequency divider becomes a median value.

Images