WO2018029929A1 - Momentum detection device - Google Patents

Abstract

This momentum detection device has a vibrating body and a drive control unit for driving the vibrating body. The drive control unit samples a drive detection signal expressing displacement in the driving direction of the vibrating body at a first clock; generates the first clock on the basis of the sampled drive detection signal such that the length of each period varies; and applies a drive signal having a period of the same length as the total length of a prescribed number of periods, greater than or equal to two, of the first clock to the vibrating body for the purpose of driving the vibrating body.

Description

Inertial detection device Import by reference

This application claims the priority of Japanese Patent Application No. 2016-155905, filed on August 8, 2016, and is incorporated into the present application by referring to its contents.

The present invention relates to inertia detection technology.

A vibration-type inertial sensor (hereinafter sometimes referred to as an inertial detection device) is a type of inertial sensor that detects physical quantities such as acceleration or angular velocity of an object using changes in vibration amplitude or vibration frequency of an inertial body. Sensor. The vibration type angular velocity sensor is capable of observing the state of an object such as a change in angular velocity and a tilt angle exerted by a substance. The vibration type inertial sensor can be used for various purposes such as control of vehicles such as automobiles, attitude control or attitude detection of unmanned airplanes or remote control robots, observation of sound waves or seismic waves, acquisition of maintenance information on aged infrastructure, installation on smartphones, etc. Used for applications. In recent years, there has been a growing need for automatic driving technology for automobiles, and inertia sensors are being developed as an element constituting an automatic driving system.

There is a capacitance detection type as the detection principle of the inertial sensor. In the capacitance detection type, a physical quantity is detected based on a change in capacitance between electrodes constituting the inertial body of the sensor element. The capacitance is detected by applying an AC pulse signal called a carrier wave. The capacity detection type inertial sensor can be realized as a MEMS sensor at a small size and at a low price by applying a MEMS (Micro Electro Mechanical Systems) structure, and therefore, its use is expanding. Since the sensor element uses a material such as silicon and has a high affinity with the detection circuit, there is a manufacturing advantage.

As a method for improving detection accuracy in an inertial sensor, there is a method of servo-controlling the inertial body of the sensor element. This servo control is a control for applying a servo force to the inertial body in order to control the displacement when the inertial body is displaced in the inertial coordinate system in accordance with a change in physical quantity. In other words, this servo control is a control for applying a servo voltage to the inertial body from the circuit unit to give a servo force so that the inertial body is in a suitable vibration state.

Japanese Patent Laid-Open No. 11-201850 (Patent Document 1) is cited as an example of the prior art relating to a capacitance detection type and servo control type inertial sensor. Patent Document 1 describes that a physical quantity detection device includes a signal processing circuit that outputs a feedback voltage, carrier wave signal generation means, and the like.

Patent Document 1: Japanese Patent Laid-Open No. 11-201850

In order to improve the stability of the vibration type inertial sensor, it is necessary to keep the vibration state of the inertial body constant with high accuracy. It is effective to apply a sensor element having a high Q value (Quality factor) (hereinafter referred to as a high Q product). By applying a high-Q product, the vibration state can be easily stabilized and the dissipation of the applied vibration energy can be reduced, which contributes to a reduction in power consumption. However, in order to properly control a high Q product, it is necessary to perform servo control with an AC servo signal accurately matched to the resonance frequency, and it is necessary to control the frequency of the AC servo voltage with very high accuracy. .

On the other hand, assuming that the resonance frequency of the vibration type inertial sensor element is MEMS, it is inevitable that the resonance frequency has a distribution centered on the design value due to various factors such as in-wafer variation and lot-to-lot variation. That is, a control method corresponding to the resonance frequency distribution having a certain width is required.

Also, once the servo control frequency matches the resonance frequency, the high Q product tends to increase the vibration amplitude suddenly due to its large gain. For this reason, the amplitude control of the servo voltage needs to be performed with high accuracy like the frequency.

Therefore, in order to appropriately apply a high Q product to a vibration type inertial sensor, means for generating an AC servo signal whose frequency amplitude is more precisely controlled in a wide frequency range and precisely adjusted to the resonance frequency is required. Become. In order to generate such an AC servo signal, a voltage controlled oscillator capable of controlling the frequency with high accuracy and a DAC (digital / analog converter) capable of controlling the analog voltage with high accuracy are required. However, in order to realize this, there is a problem that a complicated circuit is required, resulting in an increase in circuit area, leading to an increase in current consumption and an increase in manufacturing cost.

A representative embodiment of the present invention is an inertial detection device including a vibrating body and a drive control unit that drives the vibrating body, wherein the drive control unit is a displacement in a driving direction of the vibrating body. A drive detection signal representing the first clock is sampled with a first clock, and the first clock is generated so that the length of each cycle is different based on the sampled drive detection signal, and two or more of the first clock are generated. A drive signal having a cycle having the same length as a total of a predetermined number of cycles is applied to the vibrating body in order to drive the vibrating body.

According to a representative embodiment of the present invention, a high-Q sensor element can be applied to a capacitance detection type and servo control type vibration type inertial sensor without increasing the circuit scale. Therefore, it is possible to provide a vibration type inertial sensor with high cost at a low cost. Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is a figure which shows the control method of an angular velocity sensor. It is the figure which compared the operating point of the sensor element in Example 1 and a comparative example of this invention. It is the figure which showed that the resonant frequency and Q value of a sensor element have dispersion | variation. It is the figure which showed that the half value width of a gain curve decreased depending on the Q value of a sensor element. It is the figure which compared the in-band noise of the sensor element in Example 1 and a comparative example of this invention. It is a figure which shows the relationship between oversampling ratio, normalized noise intensity, and required DAC bit number. It is a functional block diagram of the angular velocity detection apparatus to which Example 1 of the present invention is applied. It is a figure which shows the structure of the clock generation circuit in Example 1 of this invention. It is a figure which shows the structure of the voltage control oscillation circuit in Example 1 of this invention. It is a figure which shows the structure of the voltage control current output circuit in Example 1 of this invention. It is a figure which shows the structure of the analog front end circuit in Example 1 of this invention. It is a figure which shows the structure of the delay circuit in Example 1 of this invention. It is a figure which shows the structure of the DAC circuit in Example 1 of this invention. It is a figure which shows the structure of the switch circuit in the DAC circuit in Example 1 of this invention. It is a figure which shows the structure of the switch 1 circuit in the switch circuit in Example 1 of this invention. It is a figure which shows the equivalent circuit of the sensor 1 in Example 1 of this invention. It is a figure which shows the timing relationship between the analog clock in Example 1 and the comparative example of this invention, the analog signal converted by ADC, the quadrature component after quadrature detection, and the waveform of an in-phase component. It is a figure which shows the phase relationship of the drive frequency control signal in Example 1 of this invention, a voltage control oscillation circuit output, the counter in a clock generation circuit, an analog clock, and a drive clock. It is a figure which shows the phase relationship of the drive frequency control signal in a comparative example, a voltage control oscillation circuit output, the counter in a clock generation circuit, an analog clock, and a drive clock. Phases of the analog clock source signal, the latch clock, the counter, the drive clock, the delay control clock source signal when the delay control value is 3, and the delay control clock source signal when the delay control value is 5 in the first embodiment of the present invention It is a figure which shows a relationship. The phase relationship between the output of the voltage controlled oscillation circuit, the delay control clock, the amplitude control signal, the delayed amplitude control signals 0 to 7 and the delay amplitude signal when the amplitude delay control value is 2 and the drive clock in the first embodiment of the present invention is shown. FIG. It is a figure which shows the phase relationship of the carrier wave, the analog signal in the time T1, and the analog signal in the time T2 in Embodiment 1 of this invention, and a comparative example. It is a functional block diagram of the angular velocity detection apparatus to which Example 2 of the present invention is applied. It is a figure which shows the structure of the clock generation circuit in Example 2 of this invention. It is a figure which shows the structure of the delay circuit in Example 2 of this invention. It is a functional block diagram of the angular velocity detection apparatus to which Example 3 of the present invention is applied. It is a functional block diagram of the acceleration detection apparatus to which Example 4 of the present invention is applied. It is a figure which shows the sensor in Example 4 of this invention. It is a figure which shows the equivalent circuit of the sensor in Example 4 of this invention. It is a figure which shows the time change waveform of the voltage which can be observed in the connection of the sensor element and circuit in Example 1 of this invention, and each connection pad.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

[Comparative example and general angular velocity sensor control example]

A control example of a comparative example and a general angular velocity sensor will be described with reference to FIG. The vibration type angular velocity sensor 1 (SENSOR1) 110 has nine types of electric input / output terminals in total, and controls the angular velocity sensor by applying appropriate signals to the input terminals.
Nine types of drive signals DRIVEP and DRIVEN, drive detection signals ASIGDP and ASIGDN, servo voltage signals SERVOP and SERVON, detection signals ASIGSP and ASIGSN, and carrier wave CARRY are all terminals. The above is a functional terminal provided in a general uniaxial angular velocity sensor, and when one sensor element has a plurality of detection axes, the number of terminals increases corresponding to the number of detection axes.

The drive signal is used to vibrate the drive mass 150, which is a part of the vibrating body, in the X direction shown in FIG. 1 with a constant frequency and a constant amplitude. The drive detection signals ASIGDP and ASIGDN are signals for detecting the vibration state of the drive mass 150 by changing the capacitance, and the displacement of the vibrating body in the X direction can be obtained from these signals. The carrier wave CARRY is an AC signal for detecting a change in capacitance. When an analog front end 109 described later is constituted by a sampling and holding circuit, it often operates at a frequency that is 1 or 0.5 times the carrier frequency. When low frequency noise is removed by synchronous detection, the analog front end 109 may sample and hold at a frequency 0.5 times higher.

The servo voltage signal is used to apply an electrostatic force in a direction to cancel the displacement when the detection mass 151 that is a part of the vibrating body is displaced in the Y direction perpendicular to the X direction shown in FIG. When the angular velocity RATE is applied while the driving mass 150 is oscillating at a constant frequency and a constant amplitude in the X direction, the detection mass 151 is displaced in the Y direction. This is detected by detection signal terminals that output detection signals ASIGSP and ASIGSN, and a servo signal is applied to a terminal to which a servo voltage signal is applied in order to cancel the displacement of the detection mass 151. The same carrier wave is also used to detect the displacement of the detection mass 151 by changing the capacitance. The vibration type angular velocity sensor 110 is the same type as the angular velocity sensor that is connected to and controlled by the circuit of the first embodiment of the present invention.

The drive detection signal and the detection signal are converted into a digital signal by the analog front end 109. A displacement 114 shown in FIG. 1 is a time change of a voltage waveform representing a displacement of the driving mass 150 in the X direction. The displacement 115 obtained from the detection signals ASIGSP and ASIGSN is a time change of the voltage waveform representing the displacement of the detection mass 151 in the Y direction. The displacement 115 includes a voltage waveform 118 before the servo voltage is applied and a voltage waveform 119 after the servo voltage is applied. In the state where the servo control for the detection mass 151 is working correctly, the amplitude of the detection signal becomes small as the waveform 119. This indicates that the displacement of the detection mass 151 is small.

The circuit block 112 that performs appropriate feedback control based on the displacement 114 of the drive mass generates a drive control signal 116. FIG. 1 shows a time change of the drive control signal 116. It is desirable that the phase of the drive control signal 116 is advanced by 90 degrees compared to the displacement 114. This is because when the vibration frequency of the drive mass 150 matches the resonance frequency determined by the mechanical structure of the drive mass 150, the drive mass displacement is delayed by 90 degrees with respect to the drive signal. When the driving mass 150 is driven at the resonance frequency, the energy applied for driving is converted into the oscillating motion of the driving mass 150 with a minimum loss, which contributes to a reduction in power. The drive control signal 116 is input to the digital-analog converter (DAC) 101, and drive signals DRIVEP and DRIVEN are generated. The above is a general control loop of the driving mass 150.

The circuit block 113 that performs appropriate feedback control based on the displacement 115 of the detection mass 151 outputs a sensor output SENSOROUT and a servo control signal 117. The sensor output SENSOROUT is output as an amplitude component of the signal component VSIG121 of the servo control signal 117 (showing the time change of VSIG121 in FIG. 1). The amplitude of the VSIG 121 is proportional to the arithmetic product of the time derivative V of the displacement 114 in the X direction of the driving mass 150 and RATE, and the frequency thereof is the same as that of the displacement 114. The phase of the VSIG 121 is shifted by 90 degrees compared to the displacement 114 when the delay in the analog front end 109 (ANALOG) and the circuit block 113 (YCTRL) is assumed to be zero. If the delay in the circuit block is not zero, the circuit block 113 provides an appropriate delay for the 90 degree phase shift. The quadrature component VERR 120 (showing the time change of VERR 120 in FIG. 1) is in phase with the displacement 114, and the amplitude is also proportional. The servo control signal 117 is a sum of VSIG 121 and VERR 120, which is input to the DAC 101, and SERVOP and SERVON are output. The DAC 101 may be basically the same type as that for drive control, but the number of constituent bits is generally different. The above is the control loop of the detection mass 151.

As described above, the control of the vibration type angular velocity sensor requires two loops of the drive control which is the control loop of the drive mass 150 and the detection control which is the control loop of the detection mass 151, and how these are highly accurate and highly stable. This will affect the control and stability of the angular velocity sensor output.

Referring to FIGS. 2 to 4, a description will be given of how the first embodiment can solve the problem in drive control by comparing the first embodiment with the conventional example.

FIG. 2 shows the relationship between the amplitude gain of the sensor element and the drive frequency, and the relationship between the drive frequency control signal and the drive signal frequency. In general, a sensor element is constituted by a vibrating body having a secondary transfer characteristic, and the amplitude gain is designed to take a maximum value at a resonance frequency f0. In the inappropriate control shown in FIG. 2A, since the drive frequency control value is sparse (that is, the step of the settable drive frequency value is large), the drive control is performed at a frequency close to f0 but different from f0. There is no choice but to get a sufficient amplitude gain of the sensor element. However, in the ideal control shown in FIG. 2B, since the drive frequency control value can be set sufficiently densely (that is, the step of the settable drive frequency value is sufficiently small), the amplitude of the sensor element The gain can be utilized to the maximum. Therefore, the drive amplitude can be increased with a small input energy, which contributes to low power consumption. Further, since the control frequency step is small, the error of the drive frequency control is reduced, so that the stability is improved and the signal-to-noise ratio of the sensor output can be improved. That is, in the drive frequency control, it is a problem to design a control circuit so that the control steps can be sufficiently dense according to the resonance frequency of the sensor element.

FIG. 3 schematically shows the distribution of the resonance frequency f0 and the distribution of the Q value of the sensor element. The left side of FIG. 3 shows the distribution of the resonance frequency f0, where the horizontal axis is f0 and the vertical axis is the number of sensor elements. The right side of FIG. 3 shows the distribution of the Q value, the horizontal axis is the Q value, and the vertical axis is the number of sensor elements. Due to manufacturing variations of sensor elements, the f0 and Q values have a distribution centered on the typical value TYPICAL. An ideal control is to make the controllable range 152 indicated by hatching wider than this. FIGS. 3A and 3B show examples of the controllable range 152 when ideal control and inappropriate control are performed, respectively. If a wider range of f0 and Q values can be controlled, more non-defective products can be obtained from the total number of sensor elements manufactured, which can contribute to cost reduction. Inappropriate control results in a small number of non-defective sensor elements, resulting in a decrease in the number of non-defective products and an increase in cost.

The ideal control is to reduce the frequency control error as shown in FIG. 2 and widen the controllable range as shown in FIG. 3, but this is a contradictory request. That is, assuming a certain circuit scale, the controllable range must be narrowed if the control error is reduced, and the control error must be increased if the controllable range is widened. It has been a problem with the conventional control method to achieve both of these.

The Q value will be described in a little more detail with reference to FIG. The Q value is given by the definition Q = f0 / Δf. As shown in FIG. 4B, f0 is defined as the resonance frequency, and Δf is defined as a difference between two frequency points at which the energy is halved compared to the resonance energy at the resonance frequency. That is, it can be said that the Q value increases in proportion to f0. FIG. 4A shows a relationship 153 between the Q value and Δf when a certain f0 is assumed. If a sensor element having a large Q value is used, the loss of input energy can be reduced as described above, which contributes to a reduction in power consumption. However, if the Q value is increased, Δf becomes smaller. For example, when the Q value is 10,000 or more, Δf is smaller than 1 Hz. This means that in order to properly control a sensor element having a Q value exceeding 10,000, it is necessary to perform frequency control with an error smaller than 1 Hz (that is, in steps smaller than that). As described above, when the frequency control is performed with high accuracy and the variation in f0 is assumed to be, for example, several kHz, the control does not fail, leading to an increase in the circuit scale, which has led to an increase in cost.

FIG. 5 and FIG. 6 are used to explain how the above problem is solved in the first embodiment. This is based on a method of increasing the sampling rate and reducing the control error as a method of expanding the controllable range while improving the frequency control accuracy with a circuit scale equivalent to the conventional one.

FIG. 5 is a diagram for explaining comparison of noise intensity between normal sampling and oversampling. The relationship among the gain curve 500 of the sensor element, the overall noise intensity 501 at the time of oversampling, the in-band noise intensity 503, the overall noise intensity 502 at the time of normal sampling, and the in-band noise intensity 504 is shown. The total noise intensity 501 at the time of oversampling and the total noise intensity 502 at the time of normal sampling have the same area, but the total noise intensity 501 at the time of oversampling is distributed over a wide frequency region because the sampling frequency is high. For this reason, during oversampling, the noise intensity per frequency is smaller than during normal sampling. When performing frequency control, the in-band noise intensity becomes a problem. Therefore, comparing the in-band noise intensity 503 during oversampling with the in-band noise intensity 504 during normal sampling, the in-band noise intensity 503 during oversampling Can be reduced. For example, the in-band noise can be halved by doubling the sampling rate. Based on this principle, the first embodiment reduces the frequency control error.

FIG. 6 is a diagram showing the relationship between the number of frequency control steps and the normalization error when the control sampling rate Fs is changed. The horizontal axis of the frequency control step is indicated by a power of 2, and x = 3 indicates that frequency control is performed in 2 ^ 3 = 8 steps. Since the controllable frequency range is constant, it means that the control becomes finer as the number of steps increases. When Fs is increased to 2 ^ 1 (= 2) times, 2 ^ 2 (= 4) times, etc. of the resonance frequency f0 of the sensor element, when compared with the same noise intensity, the control sampling rate Fs is increased. It shows that the number of necessary frequency control steps can be reduced. In other words, when compared with the same noise intensity, the controllable frequency range can be increased as the control sampling rate Fs is increased. Further, when compared with the same number of frequency control steps and the same controllable frequency range, the noise intensity decreases as the control sampling rate Fs increases. That is, noise intensity can be reduced by making Fs sufficiently larger than f0. By using this method, the first embodiment achieves both a wide controllable frequency range and detailed frequency control.

7 to 22, the inertial detection device according to the first embodiment of the present invention will be described. The inertial detection device according to the first embodiment is an angular velocity sensor of a capacity detection type and a uniaxial servo control system.

[(1-1) Inertial sensor_Function block]

FIG. 7 is a functional block diagram showing a configuration of the vibration type angular velocity detection device according to the first embodiment of the present invention.

The drive control circuit 100 is a circuit that performs drive control of the sensor 110. The angular velocity signal detection circuit block 143 performs feedback control of the detection mass 151 according to the input angular velocity, and calculates and outputs a sensor output SENSOROUT indicating the angular velocity. The angular velocity signal detection circuit block 143 receives the detection control signal YCTRL from the drive control circuit 100, receives the detection mass displacement outputs ASIGSP and ASIGSN of the sensor 110 in synchronization with this signal, and receives the detection control signals SERVOP and SERVON according to the detection control signals SERVOP and SERVON. This is a general angular velocity output control block that controls the detected mass and calculates and outputs the sensor output SENSOROUT.

The configuration of the drive control circuit 100 will be described in detail below. The detected mass displacement signals ASIGDP and ASIGDN from the sensor 110 are analog signals, and the analog front end 109 is a circuit that appropriately amplifies and converts them. P and N indicate that the detected mass displacement signal is a differential input to the analog front end 109. A circuit block that receives an input of the digital drive mass displacement signal DSIGD, performs quadrature detection based on the quadrature detection timing signal CTRCLK1, and outputs the in-phase component INPHASE and the quadrature phase component QUAD is a quadrature detection circuit DEMOD (106). The quadrature detection circuit 106 includes two multipliers 102. One multiplier 102 multiplies DSIGD and CTRCLK and outputs INPHASE, and the other multiplier 102 multiplies DSIGD and a clock that is 90 degrees out of phase with CTRCLK and outputs QUAD.

A circuit that outputs the frequency control signal PIDS and the amplitude control signal PIDC with the input of INPHASE and QUAD is the control circuit 105. Typically, it is composed of a PID (ProportionalifIntegral Differential) controller, and in calculating the proportional component P, the integral component I, and the differential component D, a coefficient CTRLVALS necessary for each calculation is input from the memory 111 to the control circuit 105. .

The frequency control signal PIDS is input to the clock generation circuit CLKGEN1 (104). Based on the input frequency control signal PIDS and the control multiplier CTRLVALS from the memory 111, the clock generation circuit CLKGEN1 (104) modulates CTRCLK2 serving as a latch clock of the delay circuit 103 and the drive signal modulation circuit DMOD (107). A clock DCLKD and an analog circuit clock CLKA are generated. The role and phase relationship of each clock will be described in the explanation of the operation of each circuit block.

The analog circuit clock CLKA is amplified to an appropriate analog signal by the analog driver 108 and input to the sensor 110 as a carrier wave CARRY. The analog circuit clock is a reference clock for the analog front end 109. That is, the carrier wave and the operation timing of the analog circuit are synchronized.

Next, the drive amplitude control loop will be described. The amplitude control value signal PIDC is input to the delay circuit 103 for appropriate delay. The delay circuit 103 latches PIDC with CTRCLK2, delays PIDC based on the delay information DCTR2, and outputs it as a delay drive amplitude DAMP. The drive signal modulation circuit 107 includes a multiplier 102 that multiplies DAMP and the modulation clock DCLKD, and outputs a drive modulation signal DRIVE0 as a multiplication result. The digital-analog conversion circuit DAC (101) converts DRIVE0 into drive signals DRIVEP and DRIVEN and inputs them to the sensor 110. Here, P and N represent positive and negative, and DRIVEP and DRIVEN have the same amplitude and have a phase difference of 180 degrees (that is, the amplitudes are inverted from each other).

The feature of the circuit function block described above is that there are no filters that lower the sampling rate after the analog front end 109, after the quadrature detection circuit 106, and after the control circuit 105, respectively. With this configuration, it is possible to configure a control loop without reducing the sampling rate Fs of the analog front end 109, and to reduce the noise intensity by utilizing the oversampling effect as described with reference to FIGS. In addition, since the oversampling rate Fs has an effect of reducing noise if Fs> f0, even if a filter circuit is inserted for the purpose of lowering the sampling rate as long as this condition is satisfied, it is included in the range of the first embodiment. . Here, f0 is the resonance frequency of the sensor 110.

FIG. 8 is a diagram illustrating a specific configuration example of the clock generation circuit 104 according to the first embodiment of the present invention.

The frequency control signal PIDS is input to the voltage controlled oscillation circuit VCO (122). The voltage controlled oscillation circuit 122 has a frequency variable range controlled by the voltage controlled oscillation circuit control coefficient VCTRL, and generates a clock CLK0 having a frequency corresponding to PIDS within the frequency range. In this embodiment, the voltage-controlled oscillation circuit control coefficient VCCTRL is set so that the frequency of the generated analog clock CLKA is at least twice the natural frequency of the vibration body of the sensor 110 including the drive mass 150 and the detection mass 151. Is set. For example, the voltage-controlled oscillation circuit control coefficient VCCTRL is set so that the voltage-controlled oscillation circuit 122 can generate a clock CLK0 having a frequency 16 times the natural frequency of the vibrating body according to PIDS, and the natural vibration of the vibrating body is determined from the clock CLK0. An analog clock CLKA having a frequency eight times the number may be generated (see FIGS. 17 to 20 and the like). In the present embodiment, since the length of the period of the analog clock CLKA changes every period, the frequency of the analog clock CLKA in the above description is, for example, an average calculated from the number of periods included in a certain period. May be a typical frequency.

The counter circuit 123 generates an analog clock original signal CLKA0, a modulation clock original signal DCLKD0, a K-times count clock CLKK, and an L-times count clock CLKL by counting up or counting down using CLK0 as a count clock. The counter 124 generates a clock CTRCLK10 obtained by latching and delaying DCLKD0 with CLKL based on the delay information DCTRL1.

CLKA0 is output as an analog clock CLKA through the clock buffer 125, DCLKD0 is output as DCLKD through the clock buffer 125, CLKK is output as CTRCLK2 through the clock buffer 125, and CTRCLK10 is output through the clock buffer 125 as CTRCLK1. Is output as Thus, each cycle of the analog clock CLKA has a length corresponding to the size of each sample value of the quadrature component QUAD, and the length differs for each cycle (see FIG. 17). .

FIG. 9 is a diagram illustrating a specific configuration example of the voltage controlled oscillation circuit 122 according to the first embodiment of the present invention.

The voltage control current output circuit 126 outputs a reference current IREF based on the oscillation circuit control coefficient VCTRL. The digital-analog conversion circuit 127 generates a voltage signal DAC0 based on the frequency control signal PIDS. An oscillation circuit that generates the clock CLK0 based on IREF and DAC0 is OSCGEN (128). The oscillating circuit 128 is basically a general oscillating circuit having a mechanism for adjusting the charging time of the capacitor with current and voltage and thereby changing the oscillating frequency. In the first embodiment, even if the frequency step is increased by oversampling, the noise intensity can be lowered. Therefore, the number of control steps of the voltage control current output circuit 126 and the digital / analog conversion circuit 127 may be reduced. Therefore, the circuit scale of the voltage control current output circuit 126 and the digital-analog conversion circuit 127 can be reduced, which contributes to cost reduction.

FIG. 10 is a diagram illustrating a specific configuration example of the voltage controlled current output circuit 126 according to the first embodiment of the present invention.

The voltage control current output circuit 126 has a decoder 129 that decodes VCOCRL to obtain an 8-bit output, and a current source CS (130) that determines ON / OFF of the output current by the decoder output. For example, among the 8 bits from <0> to <7>, the decoder 129 is ON only for <0> and the rest is OFF, <1: 0> is ON and the rest is OFF, or <2: 0> is ON And outputs the value that the rest is OFF. As a result, according to the output of the decoder 129, the magnitude of IREF can be changed in 8 ways from 1 CS output to 8 outputs. The voltage-controlled current output circuit shown in FIG. 10 is an example of 8-gradation current output by a 3-bit decoder, but this is an example, and the number of bits can be freely changed by the system. For example, if VCCTRL is 4 bits, the current output can be changed to 16 gradations, and if 5 bits, it can be changed to 32 gradations. However, increasing the number of bits is not preferable because the circuit scale increases. According to the first embodiment, the number of bits can be reduced due to the oversampling effect. Therefore, it is desirable to set the number of bits to the smallest within a range that can satisfy the target performance of the system.

FIG. 11 is a diagram illustrating a specific configuration example of the analog front end 109 according to the first embodiment of the present invention.

The C / V conversion circuit 131 is a circuit block that amplifies and converts the input of the analog amplitude signals ASIGDP and ASIGDN into voltage signals CVDP and CVDN, respectively. The C / V conversion circuit 131 operates in synchronization with the analog clock CLKA. As a well-known circuit system, a switched capacitor circuit having a sampling hold circuit may be applied. An amplifier circuit 132 that amplifies the differential C / V conversion circuit outputs CVDP and CVDN and outputs differential voltage signals of AMPDP and AMPDN follows the C / V conversion circuit 131. However, the amplifier circuit 132 may be inserted when the gain of the C / V conversion circuit 131 is insufficient, and may not be required when the amplification is not insufficient. The amplifier circuit 132 is preferably a fully differential amplifier that amplifies the differential input to obtain a differential output. By using a fully differential amplifier, common-mode noise can be reduced and the dynamic range can be widened. The amplifier circuit 132 also operates in synchronization with the analog clock CLKA. A circuit that converts the differential outputs AMPDP and AMPDN of the amplifier circuit 132 into a digital signal DSIGD is an analog-digital conversion circuit ADC (133). Various ADCs such as ΣΔ ADC, SAR ADC, and cyclic ADC are known as ADCs, but any ADC circuit may be applied in the first embodiment. The ADC 133 also operates in synchronization with the analog clock CLKA. All circuit blocks of the C / V conversion circuit 131, the amplifier circuit 132, and the ADC 133 are synchronized with CLKA. A unique clock may be generated based on CLKA in each circuit block, but details are omitted.

FIG. 12 is a diagram illustrating a specific configuration example of the delay circuit 103 according to the first embodiment of the present invention.

The delay circuit 103 has a configuration in which eight data latch circuits DL (134) that latch the amplitude control signal PIDC at the timing of the latch clock CTRCLK2 are connected in series. The output of each data latch circuit is an 8-bit delay amplitude control signal PIDCD <7: 0>. <0> has a delay of one clock of CTRCLK2 with respect to PIDC. Hereinafter, <1> has two clocks, <2> has three clocks, and similarly, the delay amount increases in units of CTRCLK2.

A circuit that selects one signal from PIDCD <7: 0> by DCTR 2 is a MUX circuit 135. As a result, a delay drive amplitude signal sequence DAMP having a delay designated by DCTR2 is obtained. In the example shown in FIG. 12, eight delay amounts can be set because it is assumed that the ACLK operates at a frequency eight times the sensor resonance frequency f0. In other words, it is assumed that the oversampling ratio is set to 8 times. The number of data latches 134 in series needs to be increased according to the oversampling ratio. For example, when the oversampling ratio is 16 times, a 16-stage data latch 134 is required.

Alternatively, when the oversampling ratio is 8 times, it is also possible to connect four data latches 134 in series and further comprise a circuit that can invert the polarity of the data. That is, it is also possible to provide a circuit that serializes the number of data latches that is half the oversampling ratio and finally selects whether to output the data with the polarity reversed or with the same polarity. . With this configuration, the number of data latch circuits can be reduced. By configuring the delay circuit in this way, the delay of drive amplitude control can be controlled in units of analog sampling clock, and the accuracy of drive control is improved, resulting in a stable angular velocity sensor with low noise. It will be possible.

FIG. 13 is a diagram illustrating a specific configuration of the digital-analog conversion circuit DAC according to the first embodiment of the present invention.

The decoder 137 that decodes the input of the drive modulation signal DRIVE0 selects one of the complementary signals SELP <0: m> and SELN <0: m> according to the value of DRIVE0. The complementary selection is defined as selecting K + L = m when SELP <K> and SELN <L> are selected. SELP and SELN are input to the voltage selection circuit VSEL136. The voltage selection circuit VSEL136 is configured to select and output one voltage obtained by dividing the voltage difference between the high-voltage side reference voltage VREFH and the low-voltage side reference voltage VREFL by one switch 139 by connecting the resistors RES138 in series. . The values of VREFH and VREFL are not particularly required to be the same as the power supply voltage, and are preferably set according to the sensor characteristics. The complementary output of the VSEL 136 is adjusted in output impedance and output amplitude by the analog buffer 140 and output to the sensor as drive signals DRIVEP and DRIVEN. When a high voltage is required as the driving voltage, the analog buffer 140 must also operate as a level conversion circuit, and the first embodiment includes such a case where a high voltage is output.

As described so far, since the drive signals DRIVEP and DRIVEN are generated from the in-phase component INPHASE output from the quadrature detection circuit 106, the length of one cycle is a predetermined number of cycles of the analog clock CLKA. In the embodiment, it is the same as the total length of 8 cycles).

FIG. 14 is a diagram illustrating a specific configuration example of the switch 139 included in the DAC according to the first embodiment of the present invention.

The switch 139 has a switch (sw1) 144. One switch 144 is a switch that selects whether or not to output in1 as outp when the SELP and the input signal in are input as ck1 and in1, respectively, according to the value of ck1. The other switch 144 is a switch that selects whether or not to output in2 as outn according to the value of ck2 when SELN and the input signal in are input as ck2 and in2, respectively.

FIG. 15 is a diagram illustrating a specific configuration example of the switch 144 according to the first embodiment of the present invention.

In the example of FIG. 15, the switch 144 includes a PMOS 141 that is a P-type MOS transistor and an NMOS 142 that is an N-type MOS transistor. The selection signal CK (corresponding to ck1 and ck2 in FIG. 14) is inverted in logic by the inverter and input to the gate g of the PMOS 141, and input to the gate g of the NMOS 142 without being inverted. The input of the switch 144 (corresponding to in1 and in2 in FIG. 14) is SWin, which is input to the sources s of the PMOS and NMOS, and the output SWout of the switch 130 (corresponding to outp and outn in FIG. 14) is the PMOS 141 and NMOS 142 Connected to the drain d. That is, by using PMOS and NMOS as switches, the switch 144 is configured as an analog switch that outputs all analog voltage levels between VREFH and VREFL in FIG. 13 depending on CK.

FIG. 16 is a diagram showing an equivalent circuit of the sensor 110 according to the first embodiment of the present invention.

The equivalent circuit of the sensor 110 has a configuration in which a total of eight capacitances share one terminal as an input terminal for the carrier CARRY.

Capacitances Cxfp and Cxfn including input terminals of drive voltage signals DRIVEP and DRIVEN are a positive side drive capacity and a negative side drive capacity, respectively. The electrostatic force that drives the driving mass 150 is proportional to (DRIVEP-CARRY) ^ 2- (DRIVEN-CARRY) ^ 2. The driving mass 150 is driven by this electrostatic force.

The electrostatic capacitances Cxsp and Cxsn to which the drive detection signals ASIGDP and ASIGDN are connected are a positive drive detection capacitor and a negative drive detection capacitor, respectively. The displacement of the driving mass 150 can be detected by Cxsp-Cxsn.

The electrostatic capacities Cyfp and Cyfn to which the servo voltage signals SERVOP and SERVON are connected are a positive servo capacity and a negative servo capacity, respectively. The electrostatic force applied when servo-controlling the detection mass 151 is proportional to (SERVOP-CARRY) ^ 2- (SERVON-CARRY) ^ 2.

Capacitances Cysp and Cysn to which the detection signals ASIGSP and ASIGSN are connected are a positive-side detection capacitor and a negative-side detection capacitor, respectively. The displacement of the detection mass 151 can be detected by Cysp-Cysn.

[Operation waveform of Example 1]

The internal operation waveforms of the circuit of the first embodiment will be described with reference to FIGS. When necessary, the characteristics of the circuit operation of the first embodiment become clear by comparing with the comparative example.

FIG. 17 is a diagram schematically showing operation waveforms of the quadrature detection circuit 106 in the first embodiment and the comparative example of the present invention.

In order to explain the characteristics of the first embodiment, the operation waveform of the present embodiment shown in FIG. 17A is compared with the comparative example shown in FIG. These diagrams show the relationship among the analog clock CLKA, the drive amplitude information DSIGD digitally converted by the ADC, the quadrature phase component QUAD, and the in-phase component INPHASE in each example. Each data point is indicated by a dot, and the timing of the DSIGD data point is the same as the rising edge of CLKA. This indicates that data is being sampled at the rising edge of the analog clock CLKA. As apparent from the fact that there are 8 data points for one DSIGD period and the DSIGD period is the resonance oscillation period of the drive mass, FIG. 17 shows an example of a waveform when the oversampling ratio is 8 times. When performing normal quadrature detection, a DC component and a second harmonic component appear in the cos (cosine) component, and a second harmonic component (2α) appears in the sin (sine) component, as shown in Equation (1).

In the first embodiment, the QUAD that is the second harmonic component of the sine and the INPHASE that is the second harmonic component of the cosine are not filtered, and the oversampling ratio is 8 times. As a result, since the frequency control value can take a different value for each data point, in the first embodiment, the time interval of each sampling point, that is, the period of the analog clock CLKA is different for each clock. On the other hand, in the comparative example, in the QUAD signal and the INPHASE signal, since the second harmonic component is removed by the filter, there is only one control point during the resonance period. Therefore, the clock cycle of CLKA does not change at least during one resonance cycle. The greatest difference between the first embodiment and the comparative example is the number of QUAD and INPHASE data points. As a result, in the first embodiment, the analog sampling interval changes even within one resonance cycle. As shown in FIG. 7, a signal obtained by setting CLKA to a desired voltage amplitude by an analog buffer is a carrier CARRY. Therefore, the same characteristics as those of CLKA are observed in the time waveform of the carrier.

FIG. 18 is a diagram illustrating operation waveforms of the clock generation circuit CLKGEN in the first embodiment.

The counter COUNT0 is configured as a count-up type counter, and performs a count-up operation at the rising edge of CLK0. Here, an example of a 3-bit counter (count from 0 to 7) is shown. The number of bits of the counter may be changed depending on the design. The analog clock source signal CLKA0 is a second harmonic of CLK0 (that is, a signal whose one cycle corresponds to two cycles of CLK0), and the drive clock source signal DCLKD0 is a sixteenth harmonic of CLK0. According to FIG. 17, since the data of the quadrature phase component QUAD is updated at the rising edge of CLKA, the frequency control signal PIDS is also updated at the rising edge of CLKA0 which is the original signal of CLKA. The oscillation frequency of CLK0 changes according to PIDS, and the count-up timing also changes accordingly. In other words, the time interval for counting up changes. Thus, a period of one period of CLKD0 is represented by 0.5 * T03 + 2 * (T10 + T11 + T12) + 1.5 * T13 as shown in FIG.

FIG. 19 is a diagram showing operation waveforms of a conventional clock generation circuit. This is a comparative example for comparison with the operation waveform of the first embodiment shown in FIG.

In the comparative example shown in FIG. 19, since the PIDS is updated only once in one cycle of DCLKD0, the count-up timing of the counter does not change during one cycle of DCLKD0, and therefore one cycle of DCLKD0. Is expressed as 0.5 * T0 + 7.5 * T1.

When the time of one period of DCLKD0 is expressed, in the first embodiment, it is expressed by the sum of five types of times T03, T10, T11, T12 and T13, whereas in the comparative example, it is expressed by two types of times T0 + T1. Therefore, in the comparative example, the gradation of time that can be expressed is sparse compared to the first embodiment. In other words, in the comparative example, when performing drive control, the gradation of frequency control becomes sparse, which means that an error from the resonance frequency of the sensor increases. Since the number of bits of the counter is exactly the same in the first embodiment and the comparative example, the first embodiment shows that the noise is reduced by devising the control method without increasing the circuit scale.

FIG. 20 is a diagram illustrating a method of generating the delay clock CTRCLK10 in the clock generation circuit CLKGEN based on the waveforms.

CTRCLK10 is a clock generated by delaying the drive clock original signal DCLKD0 based on the delay amount control multiplier DCTRL1. As is clear from the fact that the eighth harmonic of CLKA0 is DCLKD0, FIG. 20 shows an example in which the oversampling ratio is eight. Therefore, the delay amount must be set from 0 to 7 in units of one clock of CLKA0. Therefore, in the first embodiment, the delay information is generated by the 3-bit counter COUNT1 using CLKA0 as the count-up clock, and DCLKD0 is latched at the rising edge of the latch clock CLKL at the timing when the value of COUNT1 coincides with DCTRL1. To do. As a result, if the delay amount setting for quadrature detection is 8 times the oversampling ratio, all values from 0 to 7 can be set, which contributes to improving the timing accuracy of quadrature detection. Since the oversampling ratio changes depending on the design, for example, when it is 16 times, the clock generation circuit CLKGEN needs to be designed so that all the delay amounts from 0 to 15 can be set.

FIG. 21 is a diagram showing an example of operation waveforms of the delay circuit 103 in FIG.

As shown in FIG. 17, the value of the amplitude control signal PIDC is updated at the rising edge of CLKA0 for use in control without removing the second harmonic component in INPHASE. This is latched in each data latch at the rising edge of the latch clock CTRCLK2 of the data latch train, and its outputs are PIDCD <0> to <7>. For example, when the delay setting value DCTR2 = 2, since PIDCD <2> is selected by the MUX, data delayed by three clocks of CLKA0 compared to PIDC is output as the output DAMP of the delay circuit 103 as shown in FIG. The Since DCLKD0 is an eighth harmonic of CLKA0 as in FIG. 20, FIG. 21 shows an example with an oversampling ratio of eight. Therefore, fine delay settings are possible because there are delay settings from 0 to 7. This improves the stability of the drive amplitude control and contributes to the stabilization of the sensor output.

FIG. 22 shows the reason why oversampling is possible in Example 1 by comparing with the comparative example.

Normally, the driving mass 150 of the angular velocity sensor is stationary when the power is turned off. Therefore, after the power is turned on, the drive control circuit 100 controls the drive mass 150 from the stationary state to the resonant state. There is a possibility that the vibration frequency of the drive mass 150 is larger or smaller than the resonance frequency in the stage before reaching the resonance state. In the comparative example shown in FIG. 22A, since the CARRY frequency is always constant, if the vibration state of the driving mass 150 is different between the vibration at the time T1 and the vibration at the time T2, the oversampling ratio is different. The oversampling ratio in the comparative example is 11 times at time T1 and 8 times at time T2. If the oversampling ratio changes with time, the control error does not become constant, so that stable control cannot be performed. As a result, the sensor output becomes unstable or the noise intensity increases.

On the other hand, in Example 1 shown in FIG. 22B, since the CARRY frequency also fluctuates in accordance with the vibration state of the driving mass 150, the oversampling ratio remains constant at 8 times at both time T1 and T2. For this reason, the control error can always be kept constant, and as a result, stable control becomes possible. In other words, the first embodiment has a configuration equivalent to a PLL (Phase Locked Loop) including a sensor in a control loop, as is apparent from the configuration shown in FIG. For this reason, even if the resonance frequency of the sensor element changes, it is possible to maintain the oversampling ratio set in the circuit even in a situation where the vibration state of the drive mass gradually changes from the sensor power ON. It is very different from the comparative example. This also makes it possible to construct a control loop based on the basic principle of noise reduction by oversampling.

FIG. 30 is a schematic diagram illustrating an electrical signal applied to the sensor element from the control circuit according to the first embodiment.

The first feature is that the cycle of the carrier wave CARRY continues to change during one cycle of the drive voltages DRIVER and DRIVEN. Servo voltages SERVOP and SERVON are also output so that their values change at the same timing as the change in CARRY. On the other hand, the drive mass displacement detection signals ASIGDP and ASIGDN, and the detection mass displacement detection signals ASIGSP and ASIGSN are input to the C / V conversion circuit, so that a constant level is obtained due to the virtual grounding of the operational amplifier in the C / V conversion circuit. Observed as an unchanging waveform.

Example 2 will be described with reference to FIGS. Except for the differences described below, each part of the system of the second embodiment has the same functions as the parts denoted by the same reference numerals of the first embodiment shown in FIGS. 1 to 22 and 30. Those explanations are omitted.

FIG. 23 is a functional block diagram showing the configuration of the vibration type angular velocity detection device according to the second embodiment of the present invention.

In the first embodiment, the concept of oversampling is introduced to control the drive mass 150. However, in the second embodiment, the same concept is applied to the control loop of the detection mass 151, which is different from the first embodiment. . In the angular velocity detection circuit block 200, compared with the drive control circuit 100 in the first embodiment, the delay circuit 203 receives two inputs of the error component ERR and the signal component SIG, and outputs two signals of the delay error component ERRD and the delay signal component SIGD. This is different from the drive control circuit 100 of the first embodiment. Further, the configuration of the modulation circuit SMOD202 that modulates ERRD and SIGD with the modulation clock DCLKD is also different from the drive signal modulation circuit DMOD102 of the first embodiment. Further, unlike the control of the driving mass 150, the control of the detection mass 151 needs to apply a servo signal so as to cancel the error component and the signal component, respectively, and therefore there is an adder SUM201 that adds the error component and the signal component. . A general drive control circuit (DRVCTRL2) 205 that receives the drive mass displacement detection signals ASIGDP and ASIGDN and generates drive voltages DRIVEP and DRIVEN outputs a drive control timing signal XCTRL to the angular velocity detection circuit 200. The clock generation circuit 204 that generates various clocks is also different from the first embodiment. The angular velocity detection circuit block 200 according to the second embodiment includes a circuit block LOGIC 206 that performs a necessary calculation on the signal component SIG in order to output an angular velocity signal.

FIG. 24 is a diagram illustrating a specific configuration of the clock generation circuit 204 according to the second embodiment of the present invention.

8 is different from the clock generation circuit 104 shown in FIG. 8 only in that there is no VCO, and the others have the same configuration. In the clock generation circuit 204, since the drive control timing signal XCTRL becomes the count clock of the counter, the VCO is unnecessary. The drive control timing signal XCTRL is a signal generated by the general drive control circuit 205 and indicating the control timing for driving the drive mass 150. For example, the drive control timing signal XCTRL may be a signal similar to CLK0 shown in FIG. .

FIG. 25 is a diagram showing a specific configuration of the delay circuit 203 according to the second embodiment of the present invention.

Since the delay circuit 203 requires two systems of input / output, the delay circuit 203 has two delay circuits 103 shown in FIG.

Since the displacement signal in the Y direction detected from the sensor is modulated by the driving frequency of the vibrating body, it is necessary to perform synchronous detection that is accurately matched to the driving frequency in order to obtain the angular velocity. According to the present embodiment, the angular velocity can be obtained by performing synchronous detection accurately matched to the drive frequency.

Example 3 will be described with reference to FIG. Except for the differences described below, each part of the system of the third embodiment has the same functions as the parts denoted by the same reference numerals of the first and second embodiments shown in FIGS. 1 to 25 and FIG. Therefore, those descriptions are omitted.

FIG. 26 is a block diagram illustrating a configuration of the vibration type angular velocity detection device according to the third embodiment of the present invention.

In the first embodiment, oversampling is performed only by controlling the drive mass 150, and the control of the detection mass 151 is a conventional method. On the other hand, in the second embodiment, oversampling is performed only by the control of the detection mass 151, and the control of the drive mass 150 is a conventional method. On the other hand, the apparatus of the third embodiment includes an angular velocity sensor controller 300 that performs oversampling by both the control of the driving mass 150 and the control of the detection mass 151. The angular velocity sensor controller 300 includes both the drive control circuit 100 shown in FIG. 7 and the angular velocity detection circuit 200 shown in FIG.

The drive control timing signal XCTRL of the present embodiment is a signal indicating the control timing for driving the drive mass 150 generated by the drive control circuit 100 similar to that of the first embodiment. For example, the CLK0 shown in FIG. The same signal may be used.

According to the present embodiment, even when the drive control circuit according to the first embodiment is used, the angular velocity can be obtained by performing the synchronous detection accurately matched to the drive frequency.

Embodiment 4 will be described with reference to FIGS. Except for the differences described below, each part of the system of the fourth embodiment has the same functions as the parts denoted by the same reference numerals in the first to third embodiments shown in FIGS. 1 to 26 and 30. Therefore, those descriptions are omitted.

In Examples 1 to 3, an angular velocity sensor is shown as an example of a vibration type inertial sensor to which the present invention is applied. In Example 4, an acceleration sensor is shown as another example of a vibration type inertial sensor.

FIG. 27 is a functional block diagram showing the configuration of the vibration-type acceleration detection device according to the fourth embodiment of the present invention.

The acceleration detection device of the fourth embodiment shown in FIG. 27 has no angular velocity detection circuit 143 as compared with the first embodiment shown in FIG. 7, and the control target sensor is a resonance frequency change type acceleration sensor 400. Different. The sensor 400 is an acceleration sensor that outputs a detected acceleration as the resonance frequency changes when acceleration is applied to a state in which the detection mass 401 (see FIG. 28) is maintained in a constant vibration state. The configuration of the control circuit 411 is different from that of the angular velocity sensor shown in FIG. 7 except that a circuit block 410 that calculates and outputs acceleration information by inputting the amplitude control signal PIDC and the frequency control signal PIDS is added. Same as the drive mass control loop.

FIG. 28 is a diagram illustrating an example of a sensor element of the vibration type acceleration sensor according to the fourth embodiment of the present invention.

Since the sensor 400 of the fourth embodiment is a capacity detection type, a carrier wave CARRY is necessary, and this is input to the detection mass 401.

FIG. 29 is a diagram showing an equivalent circuit of the sensor 400 shown in FIG.

The equivalent circuit of the sensor 400 has a configuration in which a total of four capacitances share one terminal as an input terminal for the carrier CARRY. Capacitances Cxfp and Cxfn including input terminals of drive voltage signals DRIVEP and DRIVEN are a positive side drive capacity and a negative side drive capacity, respectively. The electrostatic force that drives the detection mass 401 is proportional to (DRIVEP-CARRY) ^ 2- (DRIVEN-CARRY) ^ 2. The detection mass 401 is driven by this electrostatic force so as to maintain a constant vibration state. Capacitances Cxsp and Cxsn to which ASIGDP and ASIGDN are connected are a positive detection capacitance and a negative detection capacitance, respectively. The displacement of the detection mass 401 can be detected by Cxsp-Cxsn.

According to the fourth embodiment, it is possible to apply a high-Q sensor element without increasing the circuit scale even when the inertial detection device is an acceleration detection device.

In addition, this invention is not limited to the above-mentioned Example, Various modifications are included. For example, the above-described embodiments have been described in detail for better understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. Further, the control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown.

Claims (9)

1. An inertial detection device having a vibrating body and a drive control unit that drives the vibrating body,
   The drive control unit
   A drive detection signal representing a displacement in the drive direction of the vibrator is sampled by a first clock
   Based on the sampled drive detection signal, the first clock is generated so that the length of each period is different,
   An inertial detection device, wherein a drive signal having a cycle having the same length as a total of a predetermined number of cycles of two or more of the first clock is applied to the vibrating body in order to drive the vibrating body.
2. The inertial detection device according to claim 1,
   The drive control unit
   Quadrature detection of the drive detection signal sampled by the first clock;
   The inertial detection device according to claim 1, wherein each cycle generates the first clock having a length corresponding to the size of each sample value of the quadrature phase component obtained by the quadrature detection.
3. The inertial detection device according to claim 2,
   The inertial detection device, wherein the drive control unit generates the first clock so that a frequency of the first clock is twice or more a natural frequency of the vibrating body.
4. The inertial detection device according to claim 3,
   The inertial detection device, wherein the drive control unit applies a signal having the same cycle as the first clock to the vibrating body as a carrier wave signal for detecting displacement of the vibrating body.
5. The inertial detection device according to claim 2,
   The inertial detection apparatus, wherein the drive control unit generates an output signal indicating an acceleration applied to the vibrating body based on the quadrature phase component and the same phase component obtained by the quadrature detection.
6. The inertial detection device according to claim 1,
   An inertial detection device further comprising an angular velocity detection unit that generates an output signal indicating an angular velocity applied to the vibrating body based on a detection signal representing a displacement of the vibrating body in a direction orthogonal to the driving direction. .
7. The inertial detection device according to claim 6,
   The angular velocity detector
   Sampling the detection signal with a second clock generated based on a signal indicating timing of drive control of the vibrator by the drive control unit;
   Quadrature detection of the drive detection signal sampled by the second clock;
   Based on the in-phase component obtained by the quadrature detection, an output signal indicating an angular velocity applied to the vibrator is generated,
   A servo signal having a period having the same length as the sum of two or more predetermined numbers of periods of the second clock is applied to the vibrating body in order to cancel the displacement of the vibrating body in a direction orthogonal to the driving direction. An inertia detection device characterized by that.
8. An inertial detection device having a vibrating body, a drive control unit that drives the vibrating body, and an angular velocity detection unit,
   The angular velocity detector
   Sampling a detection signal representing a displacement in a direction orthogonal to the driving direction of the vibrating body with a second clock generated based on a signal indicating timing of driving control of the vibrating body by the drive control unit;
   Quadrature detection of the drive detection signal sampled by the second clock;
   Based on the in-phase component obtained by the quadrature detection, an output signal indicating an angular velocity applied to the vibrator is generated,
   A servo signal having a period having the same length as the sum of two or more predetermined numbers of periods of the second clock is applied to the vibrating body in order to cancel the displacement of the vibrating body in a direction orthogonal to the driving direction. An inertia detection device characterized by that.
9. An inertial detection device having a vibrating body and a drive control unit that drives the vibrating body,
   The drive control unit
   A drive detection signal representing a displacement in the drive direction of the vibrator is sampled by a first clock
   Quadrature detection of the drive detection signal sampled by the first clock;
   Each cycle generates the first clock having a length corresponding to the size of each sample value of the quadrature phase component obtained by the quadrature detection;
   An inertial detection device, wherein a drive signal having a cycle having the same length as a total of a predetermined number of cycles of two or more of the first clock is applied to the vibrating body in order to drive the vibrating body.

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