JP5367904B2 - パネル配列 - Google Patents
パネル配列 Download PDFInfo
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- JP5367904B2 JP5367904B2 JP2012502088A JP2012502088A JP5367904B2 JP 5367904 B2 JP5367904 B2 JP 5367904B2 JP 2012502088 A JP2012502088 A JP 2012502088A JP 2012502088 A JP2012502088 A JP 2012502088A JP 5367904 B2 JP5367904 B2 JP 5367904B2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/02—Arrangements for de-icing; Arrangements for drying-out ; Arrangements for cooling; Arrangements for preventing corrosion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/0006—Particular feeding systems
- H01Q21/0025—Modular arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/0087—Apparatus or processes specially adapted for manufacturing antenna arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
- H01Q21/061—Two dimensional planar arrays
- H01Q21/065—Patch antenna array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
- H01Q9/0414—Substantially flat resonant element parallel to ground plane, e.g. patch antenna in a stacked or folded configuration
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49016—Antenna or wave energy "plumbing" making
- Y10T29/49018—Antenna or wave energy "plumbing" making with other electrical component
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Variable-Direction Aerials And Aerial Arrays (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Details Of Aerials (AREA)
- Transceivers (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
(a)PWBを有する複数の回路基板の各々の上の全層を撮像する工程と、
(b)複数の回路基板の各々の上の全層をエッチングする工程と(複数の回路基板の少なくともいくつかの層上のアンテナ要素とRFマッチングパッドとをエッチングする工程を含む)、
(c)回路基板を被覆して被覆された回路基板組立体を提供する工程と、
(d)被覆された回路基板組立体に穿孔する工程であって、孔の各々が被覆された回路基板組立体の最上層から被覆された回路基板組立体の最下層に延在する、工程と、
(e)被覆された回路基板組立体内に穿かれた孔の各々をめっきする工程と、
(f)被覆された回路基板組立体の外部表面上に複数のフリップチップ回路を配設する工程と、
を含む。
(1)走査盲目性(scan blindness)を誘発する表面波モードの抑制(誘電体スラブ上の放射要素と誘電体スラブ内で支持された案内モードとの間の結合による)、
(2)並行した平面モードの抑制(非同期のRFストリップライン構成による)、
(3)ユニットセル間のRF絶縁、
(4)論理電力回路からのRF回路の電気絶縁(従ってそれは同層上にプリントされるはずのRF,電力、論理回路の能力という結果となり、その結果、多層パネル内の層の全数を減らす)、
(5)給電層とRFビーム形成器に対するいくつかのRFビア伝送のための垂直伝送(これはまた、ユニットセル内のスペースを省き、配列が大きな走査量を超えて動作することを所望するとき重要となる更にタイトなユニットセルのパッキングを可能にする)。
(1)多層PWBを備えるすべての回路基板上の全層を撮像しエッチングする、
(2)回路基板のすべてを被覆し被覆されたPWBを提供する(単一の被覆段階は、本来なら多数の被覆サイクルを備えたサブ組立体の整合を省き、その結果、製造時間とコストを減らし、被覆に先立ち各層は検査されて歩留まりを改善する)、
(3)被覆されたPWBの最上層と最下層とを穿孔しめっきする(単一の穿孔操作で作られるすべてのRF,論理及び電力の相互接続部とすべての孔は固体の多層被覆を製造して充填される)
(4)PWBの外部表面上にすべての能動型及び受動型の構成要素をピックアンドプレース(pick and place)する、
(5)半田リフローしてすべての能動型及び受動型の構成要素をPWBの外部表面に結合する。
(1)コスト対性能というトレードオフを、RF CMOS、SiGe、GaAs、GaN、SiCという広範囲の能動型電子部品技術からの選択可能にすること、
(2)各送信/受信(T/R)チャネルのための個別のパッケージを省くこと、
(3)パネルの背面(能動型電子部品の側)に金属カバーを結合すること、
(4)周囲環境からの影響を防ぐ保護コーティング(environmental conformal coating)を適用すること、
(5)DC及び論理信号のために「柔軟性を有する」回路を埋め込むこと(その結果、DC、論理コネクタ材料の出費と組立コストとを省く)、
(6)配列の空冷を使用可能にすること(それにより、液体冷却等の更なる高価なアプローチを省く)。
(a)各サブ組立体262,310,312は、別個にテストされ、所望の電気的及び/又は機械的な性能特性に適合しない或いは凌ぐことのない任意のサブ組立体262,310,312は特定されて、修理されるか、UMLAを形成するために使用されないであろう。
(b)各サブ組立体310,312は、別個にテストされ、所望の電気的及び/又は機械的な性能特性に適合しない或いは凌ぐことのない任意のサブ組立体310,312は特定されて、修理されるか、UMLBを形成するために使用されないであろう。
(c)サブ組立体262,310,312の別個の製造は、各サブ組立体の製造工程が、そのサブ組立体の最大歩留まりを求めて個別に最適化されることを可能にする。
(d)既知の「良好な」サブ組立体310,312だけがUMLBを製造するために使用されるので、これは高歩留まりのUMLB製造工程という結果となる。
(e)既知の「良好な」サブ組立体262,310,312だけがUMLAを製造するために使用されるので、これは高歩留まりのUMLA製造工程という結果となる。
(f)それから結合層を介して固定されるサブ組立体262,310,312の別個の製造は、各サブ組立体262,310,312のための結合接着剤と結合温度の更に広範な選択という結果となり、各サブ組立体262,310,312のための改善された機械的な性能に導く。
その結果、UMLA260のために開発された製造及び組立のアプローチは、製造歩留まりを著しく改善する堅牢な機械的デザインを生成する。
(1)表面波モードの抑制(誘電体スラブ上の放射要素及び誘電体スラブ内に支持された案内モード間の結合に起因する走査盲目性を引き起こす恐れがある)、
(2)平行した平面モードの抑制(非対称性のRFストリップライン構成に起因する)、
(3)ユニットセル間のRF絶縁、
(4)論理及び電力回路からのRF回路の絶縁(最終的に同層上にプリントされるはずのRF、電力及び論理回路の能力という結果となり、その結果、多層パネル内の層の全数を減らす結果となる)、
(5)給電層とRFビーム形成器のためのいくつかのRFビア伝送のための垂直伝送(これはまたユニットセル内のスペースを節約し、配列が大走査量を超えて動作することを所望するときに重要となる更にタイトなユニットセルパッケージを可能にする)。
ある実施形態では、導波ケージは、層534b、530b間のウィルキンソン型給電伝送、及び、層534b、542b間のRFビーム形成器伝送のためのRF信号分配のための垂直伝送として機能する。
〔態様1〕
複数の回路基板で構成される多層プリント配線基板(PWB)で提供されるパネル配列を製造する方法であって、
(a)前記PWBを有する各回路基板上の全層を撮像する工程と、
(b)RFマッチングパッドをエッチングする工程と、エッチングされた各層を検査する工程とを含み、前記PWBを有する各回路基板上の全層をエッチングする工程と、
(c)プレプレグ材料を前記回路基板の各々の間に挿入する工程を含み、前記複数の回路基板の各々を整合する工程と、
(d)前記回路基板を被覆して被覆回路基板組立体を提供する工程であって、当該回路基板を所定温度に加熱する工程と、当該回路基板に所定圧力を所定時間だけ印加する工程とを有する、工程と、
(e)前記被覆された回路基板組立体に第1の複数の孔を穿つ工程であって、当該第1の複数の孔の各々が当該被覆回路基板組立体の最上層から最下層に延在し、当該被覆されたプリント回路基板組立体が、アンテナ要素と、前記少なくともひとつのアンテナ要素に結合したRFアンテナ給電回路と、RF電力分配回路と、DC電力分配回路と、論理信号分配回路と、を有する、工程と、
を有する方法。
〔態様2〕
態様1に記載の方法は、
前記被覆回路基板組立体内に穿かれた孔の各々をめっきして、RF、DC電力、及び/又は、論理回路の間に電気的相互接続部を完成する工程(f)を更に有する、方法。
〔態様3〕
態様2に記載の方法は、
前記複数のすべての孔の各々を充填して、固体の多層被覆回路基板組立体を提供する工程(g)を更に有する、方法。
〔態様4〕
態様2に記載の方法は、
前記固体の多層被覆回路基板組立体の外部表面上に電気的構成要素を配設する工程(h)を更に有する、方法。
〔態様5〕
態様4に記載の方法は、
(i)半田リフロー動作を実行し、電気部品を前記固体の被覆回路基板組立体の外部表面に結合する工程と、
(j)前記電気部品の少なくともいくつかの上方に金属カバーを結合する工程と、
(k)前記電気部品が配設される前記固体の多層被覆回路基板組立体の前記外部表面の上方に保護コーティングを適用する工程と、
を更に有する、方法。
〔態様6〕
態様5に記載の方法は、
ウィルキンソン型電力デバイダ回路を有する全RF層上にインク抵抗器を追加する工程を更に有する、方法。
〔態様7〕
態様6に記載の方法は、
前記電気部品は、前記固体の多層被覆回路基板組立体の前記外部表面に直接に結合されたフリップチップ回路である、方法。
〔態様8〕
態様4に記載の方法は、
ヒートシンクをフリップチップ回路上方に搭載する工程を更に有する、方法。
〔態様9〕
態様8に記載の方法は、
ヒートシンクを前記フリップチップ回路上方に搭載する工程は、液体冷却されたブレーズメントを当該フリップチップ回路上方に搭載する工程を有する、方法。
〔態様10〕
第1及び第2の対向する表面を有する多層被覆回路基板組立体であって、複数の回路基板で構成され、当該多層被覆回路基板組立体の前記第1表面を通じて放射するためにその上に配設された複数の放射アンテナを有する当該回路基板の少なくとも第1のひとつと、その上に配設されたRF給電回路を有する当該回路基板の少なくとも第2のひとつと、その上に配設された論理回路を有する当該回路基板の少なくとも第3のひとつと、その上に配設されたDC回路を有する当該回路基板の少なくとも第4のひとつと、を備え、当該多層被覆回路基板組立体の前記第1表面が当該多層被覆回路基板組立体の最上層に対応し、当該多層被覆回路基板組立体の前記第2表面が当該多層被覆回路基板組立体の最下層に対応し、当該多層被覆回路基板組立体の当該最上層から当該最下層に延在する第1の複数のめっきされたスルーホールであって前記放射アンテナ要素の回りに導波ケージを形成する第1の複数のめっきされたスルーホールを更に含む、多層被覆回路基板組立体と、
前記最下層上に配設された複数のフリップチップ回路と、
を有する、パネル配列。
〔態様11〕
態様10に記載のパネル配列は、
前記フリップチップ回路の上方に配設されたヒートシンクを更に有する、パネル配列。
〔態様12〕
態様11に記載のパネル配列は、
前記多層被覆回路基板組立体上のDC及び論理回路に電気結合された1又は2以上の柔軟性を有する回路を更に有する、パネル配列。
〔態様13〕
態様12に記載のパネル配列は、
前記多層被覆回路基板組立体上のRF回路に電気結合された1又は2以上のRFコネクタを更に有する、パネル配列。
〔態様14〕
態様13に記載のパネル配列は、
前記フリップチップ回路の上方に配設されたヒートシンクを更に有する、パネル配列。
〔態様15〕
態様14に記載のパネル配列は、
前記ヒートシンクが液体冷却されるブレーズメントとして提供される、パネル配列。
〔態様16〕
パネル配列を形成する多層プリント配線(PWB)であって、
複数のプリント回路基板(PCB)であって、その上に配設された第1の複数の放射アンテナ要素を有する当該PCBの少なくとも第1のひとつと、その上に配設され前記複数の放射アンテナ要素に電気結合されたRF給電回路を有する当該PCBの少なくとも第2のひとつと、その上に配設された論理回路を有する当該PCBの少なくとも第3のひとつと、その上に配設されたDC回路を有する当該PCBの少なくとも第4のひとつと、を備えた複数のプリント回路基板(PCB)と、
第1の複数の導波ケージであって、当該第1の複数の導波ケージの各々が前記第1の複数の放射アンテナ要素の各々に対応し、当該第1の複数の導波ケージの各々が前記PWBの第1最外層から当該導波ケージが配設された当該PWBの第2最外層に延在するめっきされたスルーホールから形成された、第1の複数の導波ケージと、
を備える、多層プリント配線(PWB)。
〔態様17〕
態様16に記載の多層プリント配線(PWB)は、
前記PWBの最下層上に配設された複数のフリップチップ回路を更に備える、多層プリント配線(PWB)。
〔態様18〕
態様17に記載の多層プリント配線(PWB)は、
前記フリップチップ回路の上方に配設されたヒートシンクを更に備える、多層プリント配線(PWB)。
〔態様19〕
態様18に記載の多層プリント配線(PWB)は、
前記ヒートシンクは、液体冷却されるブレーズメントとして提供される、多層プリント配線(PWB)。
Claims (12)
- 複数の回路基板で構成される多層プリント配線基板(PWB)で提供されるパネル配列を製造する方法であって、
(a)前記PWBを有する各回路基板上の全層を撮像する工程と、
(b)複数のアンテナ要素とRFマッチングパッドとをエッチングする工程と、エッチングされた各層を検査する工程とを含み、前記PWBを有する各回路基板上の全層をエッチングする工程であって、各アンテナ要素がユニットセルの一部として提供される、工程と、
(c)プレプレグ材料を前記回路基板の各々の間に挿入する工程を含み、前記複数の回路基板の各々を整合する工程と、
(d)単一の被覆段階で前記回路基板を被覆して被覆回路基板組立体を提供する工程であって、当該被覆回路基板組立体が、前記複数のアンテナ要素と、当該複数のアンテナ要素に結合したRFアンテナ給電回路と、RF電力分配回路と、DC電力分配回路と、論理信号分配回路と、を有し、当該回路基板を所定温度に加熱する工程と、当該回路基板に所定圧力を所定時間だけ印加する工程とを有する、工程と、を有する方法において、
(e)前記複数のユニットセルの各々の回りに導波ケージを形成する工程であって、前記被覆回路基板組立体に第1の複数の孔を穿つ工程であって、当該第1の複数の孔の各々が当該被覆回路基板組立体の最上層から最下層に延在する、工程と、
(f)前記被覆回路基板組立体内に穿かれた前記第1の複数の孔の各々をめっきして、当該複数のめっきされた孔の少なくとも幾つかが、RF、DC電力、及び/又は、論理回路の間に電気的相互接続部を完成し、且つ、当該複数のめっきされた孔の少なくとも幾つかが各ユニットセルの回りに前記導波ケージを形成する、工程と、
を有する方法。 - 請求項1に記載の方法は、
前記複数のすべての孔の各々を充填して、固体の多層被覆回路基板組立体を提供する工程(g)を更に有する、方法。 - 請求項2に記載の方法は、
前記固体の多層被覆回路基板組立体の外部表面上に電気的構成要素を配設する工程(h)を更に有する、方法。 - 請求項3に記載の方法は、
(i)半田リフロー動作を実行し、電気部品を前記固体の被覆回路基板組立体の外部表面に結合する工程と、
(j)前記電気部品の少なくともいくつかの上方に金属カバーを結合する工程と、
(k)前記電気部品が配設される前記固体の多層被覆回路基板組立体の前記外部表面の上方に保護コーティングを適用する工程と、
を更に有する、方法。 - 請求項4に記載の方法は、
ウィルキンソン型電力デバイダ回路を有する全RF層上にインク抵抗器を追加する工程を更に有する、方法。 - 請求項5に記載の方法は、
前記電気部品は、前記固体の多層被覆回路基板組立体の前記外部表面に直接に結合されたフリップチップ回路である、方法。 - 請求項6に記載の方法は、
ヒートシンクをフリップチップ回路上方に搭載する工程を更に有する、方法。 - 請求項7に記載の方法は、
ヒートシンクを前記フリップチップ回路上方に搭載する工程は、液体冷却されたブレーズメントを当該フリップチップ回路上方に搭載する工程を有する、方法。 - パネル配列を形成する多層プリント配線基板(PWB)であって、
請求項1に記載の方法によって製造される、多層プリント配線基板(PWB)。 - 請求項9に記載の多層プリント配線基板(PWB)は、
前記PWBの最下層上に配設された複数のフリップチップ回路を更に備える、多層プリント配線基板(PWB)。 - 請求項10に記載の多層プリント配線基板(PWB)は、
前記フリップチップ回路の上方に配設されたヒートシンクを更に備える、多層プリント配線基板(PWB)。 - 請求項11に記載の多層プリント配線基板(PWB)は、
前記ヒートシンクは、液体冷却されるブレーズメントとして提供される、多層プリント配線基板(PWB)。
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US61/163,002 | 2009-03-24 | ||
US12/484,626 US8279131B2 (en) | 2006-09-21 | 2009-06-15 | Panel array |
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EP (1) | EP2412056B1 (ja) |
JP (1) | JP5367904B2 (ja) |
AU (1) | AU2010229122B2 (ja) |
CA (1) | CA2753518C (ja) |
IL (1) | IL214771A (ja) |
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US20100066631A1 (en) | 2010-03-18 |
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CA2753518A1 (en) | 2010-09-30 |
EP2412056A1 (en) | 2012-02-01 |
TW201131890A (en) | 2011-09-16 |
CA2753518C (en) | 2014-10-14 |
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