JP5367400B2 - 半導体記憶装置、及びその製造方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
- G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
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Description
図1は、本発明の第1の実施形態に係る半導体記憶装置の構成を示す平面図である。図2は、図1に示したI−I´線に沿った半導体記憶装置の断面図である。本実施形態の半導体記憶装置は、可変抵抗素子をメモリセルに使用した抵抗変化型メモリである。
次に、半導体記憶装置を構成する各層の材料の一例について説明する。
次に、図1及び図2のように構成された半導体記憶装置の製造方法の一例について、図面を参照しながら説明する。
If ∝ N型半導体層及びP型半導体層の体積
一方、PINダイオードDに逆方向電圧を印加した場合に流れる逆電流(forward current)は、その主成分が表面リーク電流である。表面リーク電流は、PINダイオードDの表面欠陥、表面ラフネス、表面への付着物などに起因して発生し、PINダイオードDの表面領域を流れるリーク電流である。表面リーク電流は、PINダイオードDの周辺長に比例し、PINダイオードDの長さ(図2の縦方向の長さ)に反比例する。すなわち、PINダイオードDの逆電流Irは、半径rとすると、以下の式で表される。
Ir ∝ 1/∫dx/2πr
図2に示す断面形状を有するPINダイオードDは、N型半導体層13及びP型半導体層15の体積を減少させずに、PINダイオードDの中央部の周辺長を短くすることが可能となる。この結果、順電流を減少させずに、表面リーク電流を低減することができる。
3nm乃至“L−5−誤差”nm
の範囲に設定される。
第1に、下部電極16とP型半導体層15との界面の面積を広く保つことができるため、コンタクト抵抗上昇を抑制できる。同様に、バリア膜12とN型半導体層13との界面の面積を広く保つことができるため、コンタクト抵抗上昇を抑制できる。
第2に、抵抗として働く上部及び下部の高濃度層(N型半導体層13及びP型半導体層15)の体積を大きく保つことができるため、PINダイオードDの抵抗上昇を抑制できる。
第3に、PINダイオードDの中央部の周辺長を短くし、かつ、電流が流れる方向のPINダイオードDの長さを長くすることで、表面リーク電流に起因する逆方向のリーク電流を抑制できる。これら第1乃至第3の効果の結果、PINダイオードDの順電流が低減するのを防ぎつつ、逆方向のリーク電流を抑制することができる。
第2の実施形態は、第1の実施形態と異なる製造方法によって半導体記憶装置を製造するようにしている。この第2の実施形態の製造方法に起因して、ボイドの位置やPINダイオードDの形状が第1の実施形態と異なっている。
次に、図12乃至図14のように構成された半導体記憶装置の製造方法の一例について、図面を参照しながら説明する。
第3の実施形態は、第1の実施形態と異なる製造方法によって半導体記憶装置を製造するようにしている。すなわち、可変抵抗素子19への加工ダメージを低減しつつ、中央部がくびれたPINダイオードDを形成するようにしている。
第1乃至第3の実施形態で示した半導体記憶装置は、複数のワード線WLと複数のビット線BLとの交差領域に、マトリクス状に配置された複数のメモリセルMCを備えている。また、各メモリセルMCは、ワード線WLとビット線BLとの間に直列に接続された可変抵抗素子19及びPINダイオードDを備えている。
Claims (4)
- 可変抵抗素子及びダイオードを有し、かつピラー状の第1及び第2のメモリセルと、
前記第1のメモリセル及び前記第2のメモリセル間に設けられ、かつボイドを有する絶縁層と、
を具備し、
前記ダイオードは、N型半導体層、P型半導体層、及びこれらに挟まれた真性半導体層を有し、
前記真性半導体層の幅は、前記N型半導体層及び前記P型半導体層のそれよりも狭いことを特徴とする半導体記憶装置。 - 前記真性半導体層のくびれ量は、3nm乃至15nmの範囲に設定されることを特徴とする請求項1に記載の半導体記憶装置。
- 下部配線層上に、N型半導体層、P型半導体層、及びこれらに挟まれた真性半導体層を有するダイオード及び可変抵抗素子が積層されたメモリセルを形成する工程と、
前記メモリセルをピラー状に加工する工程と、
前記真性半導体層の幅を、前記N型半導体層及び前記P型半導体層のそれよりも狭くする工程と、
を具備することを特徴とする半導体記憶装置の製造方法。 - 隣接する第1のメモリセル及び第2のメモリセル間に絶縁材料を堆積することで、ボイドを有する絶縁層を形成する工程をさらに具備することを特徴とする請求項3に記載の半導体記憶装置の製造方法。
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JP2009030109A JP5367400B2 (ja) | 2009-02-12 | 2009-02-12 | 半導体記憶装置、及びその製造方法 |
US12/705,010 US8222626B2 (en) | 2009-02-12 | 2010-02-12 | Semiconductor memory device, method of manufacturing the same, and method of screening the same |
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KR20200132366A (ko) * | 2019-05-17 | 2020-11-25 | 에스케이하이닉스 주식회사 | 전자 장치 및 전자 장치의 제조 방법 |
US11348640B1 (en) | 2021-04-05 | 2022-05-31 | Micron Technology, Inc. | Charge screening structure for spike current suppression in a memory array |
US11715520B2 (en) | 2021-04-05 | 2023-08-01 | Micron Technology, Inc. | Socket structure for spike current suppression in a memory array |
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