JP5346490B2 - 半導体装置の作製方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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Description
本発明の第1の実施の形態にかかる半導体基板を図1(A)(B)に示す。図1(A)においてベース基板100は絶縁表面を有する基板若しくは絶縁基板であり、アルミノシリケートガラス、アルミノホウケイ酸ガラス、バリウムホウケイ酸ガラスのような電子工業用に使われる各種ガラス基板を適用される。その他に石英ガラス、シリコンウエハのような半導体基板も適用可能である。
また、接合層は水素又はフッ素で終端した半導体表面層でもよい。
本実施の形態では、第1の実施の形態で作製した半導体基板にさらに、別のパターンのLTSS層を作製する例を示す。図5(A)乃至(C)及び図6(A)乃至(C)はその作製工程を示す図である。
本実施の形態では、第2の実施の形態において作製した半導体基板を用いた半導体装置について図9と図10を参照して説明する。図9(A)において、ベース基板100の上にバリア層105と接合層104を介して、結晶面が{100}のLTSS層102とバリア層105と接合層404を介して、結晶面が{110}のLTSS層402とがそれぞれアイランド状に設けられている。LTSS層102及び402の膜厚は5nm乃至500nm、好ましくは10nm乃至200nmの厚さとすることが好ましい。LTSS層102及び402の厚さは、それぞれ図2(A)及び図5(A)で説明した脆化層103及び403の深さを制御することにより適宜設定できる。
101 半導体基板
102 LTSS層
103 脆化層
104 接合層
105 バリア層
301 素子形成用パターン
302 ダミーパターン
Claims (2)
- 第1のイオンを第1の単結晶半導体基板の一方の面に照射して、前記第1の単結晶半導体基板の表面から所定の深さの領域に第1の脆化層を形成し、
前記第1の単結晶半導体基板と、絶縁表面を有する基板とを、前記第1の単結晶半導体基板の一方の面と前記絶縁表面が重なるように接合し、
前記第1の単結晶半導体基板と前記絶縁表面を有する基板とを接合させた状態で熱処理を行い、前記絶縁表面を有する基板上に単結晶半導体層が形成されるように前記第1の単結晶半導体基板を分離し、
前記単結晶半導体層をエッチングすることにより、複数の第1の素子形成用パターンを形成し、
第2のイオンを第2の単結晶半導体基板の一方の面に照射して、前記第2の単結晶半導体基板の表面から所定の深さの領域に第2の脆化層を形成し、
前記第2の単結晶半導体基板の一方の面をエッチングし、複数の第2の素子形成用パターンと、複数の前記第2の素子形成用パターンの間に所定の間隔で配置された第2のダミーパターンとを、形成し、
前記第2の単結晶半導体基板と前記絶縁表面を有する基板とを、前記第1の素子形成用パターンと、前記第2の素子形成用パターン又は前記第2のダミーパターンと、が重ならないように、前記第2の単結晶半導体基板の前記第2の素子形成用パターン及び前記第2のダミーパターンの形成された面と前記絶縁表面とが重なるように接合し、
前記第2の単結晶半導体基板と前記絶縁表面を有する基板とを接合させた状態で熱処理を行い、前記絶縁表面を有する基板上に前記第2の素子形成用パターンの単結晶半導体層及び前記第2のダミーパターンの単結晶半導体層が形成されるように前記第2の単結晶半導体基板を分離することを特徴とする半導体装置の作製方法。 - 第1のイオンを第1の単結晶半導体基板の一方の面に照射して、前記第1の単結晶半導体基板の表面から所定の深さの領域に第1の脆化層を形成し、
前記第1の単結晶半導体基板と、絶縁表面を有する基板とを、前記第1の単結晶半導体基板の一方の面と前記絶縁表面が重なるように接合し、
前記第1の単結晶半導体基板と前記絶縁表面を有する基板を接合させた状態で熱処理を行い、前記絶縁表面を有する基板上に単結晶半導体層が形成されるように前記第1の単結晶半導体基板を分離し、
前記単結晶半導体層をエッチングすることにより、複数の第1の素子形成用パターン及び複数の前記第1の素子形成用パターンの間に所定の間隔で配置された第1のダミーパターンを形成し、
第2のイオンを第2の単結晶半導体基板の一方の面に照射して、前記第2の単結晶半導体基板の表面から所定の深さの領域に第2の脆化層を形成し、
前記第2の単結晶半導体基板の一方の面をエッチングし、複数の第2の素子形成用パターンを形成し、
前記第2の単結晶半導体基板と前記絶縁表面を有する基板とを、前記第1の素子形成用パターン又は前記第1のダミーパターンと、前記第2の素子形成用パターンと、が重ならないように、前記第2の単結晶半導体基板の前記第2の素子形成用パターンの形成された面と前記絶縁表面とが重なるように接合し、
前記第2の単結晶半導体基板と前記絶縁表面を有する基板とを接合させた状態で熱処理を行い、前記絶縁表面を有する基板上に前記第2の素子形成用パターンの単結晶半導体層が形成されるように前記第2の単結晶半導体基板を分離することを特徴とする半導体装置の作製方法。
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US10748934B2 (en) * | 2018-08-28 | 2020-08-18 | Qualcomm Incorporated | Silicon on insulator with multiple semiconductor thicknesses using layer transfer |
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KR20080101652A (ko) | 2008-11-21 |
EP1993126A3 (en) | 2010-06-16 |
EP1993126A2 (en) | 2008-11-19 |
JP2009004758A (ja) | 2009-01-08 |
KR101447938B1 (ko) | 2014-10-07 |
EP1993126B1 (en) | 2011-09-21 |
US7776722B2 (en) | 2010-08-17 |
US20080286953A1 (en) | 2008-11-20 |
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