JP5336589B2 - ポジティブフォトレジストを使用するダブルパターニングにより高密度柱構造を製造する方法 - Google Patents
ポジティブフォトレジストを使用するダブルパターニングにより高密度柱構造を製造する方法 Download PDFInfo
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Description
しかし、規則的に間隔をおく柱の二次元パターンの場合には、ダブルパターニング方式によってピッチは2の平方根ずつ増大する。サイドウォールスペーサ方式は、立体の柱ではなく規則的に間隔をおく円筒形の環を作るので、現状のままではまったく使いものにならない。
次に、第1のフォトレジスト層をフォトリソグラフィにより第1のフォトレジストパターンとなるようにパターニングする。液浸リソグラフィや非液浸式リソグラフィ等の適したフォトリソグラフィ法を使用できる。第1のフォトレジストパターンは、下位層上に位置する複数の相隔たる第1のフォトレジストフィーチャをなす。第1のフォトレジストフィーチャは上から見て多角形(正方形、三角形、長方形等)、楕円形、円形、不規則形等のあらゆる形状を持つ。次に、第1のフォトレジストパターンをマスクとして使用して下位層をエッチングし、第1のフォトレジストパターンとほぼ同じ形状を持つ複数の第1の相隔たるフィーチャを形成する。例えば、第1の相隔たるフィーチャは、デバイス層上に位置するマスキングフィーチャとなる。あるいは、デバイス層に直接形成されたフィーチャとなる。次に、第1のフォトレジストパターンを削除する。
複数の相隔たる端部は、デバイス層上に位置する複数の相隔たるエッジマスキングフィーチャをなす。各エッジマスキングフィーチャのサイズは第1の相隔たる各マスキングフィーチャより小さい。次に、下位デバイス層をパターニング(例えば、エッチング)するマスクとしてエッジマスキングフィーチャを使用し、デバイス層に柱形デバイスを形成する。あるいは、複数の相隔たる端部がデバイス層内に位置する複数の相隔たるエッジフィーチャをなす(つまり、端部そのものが柱形デバイスとなる)。端部は、上から見て多角形(正方形、三角形、長方形を含む)、楕円形、円形、その他不規則形等の適した形状を持つ。
マスキングフィーチャとデバイス層は等方性エッチングか異方性エッチングによりエッチングできる。エッジマスキングフィーチャは完成したデバイスに残すか、デバイス層をエッチングした後に除去する。例えば、これらのフィーチャがタングステン等の導電材を含むなら、上部電極の一部として残すことができる。
マスキング層140上には第1のフォトレジスト層を形成する。図5、6A、および6Bに見られるように、第1のフォトレジスト層は、相隔たる第1のフォトレジストフィーチャ150を有する第1のフォトレジストパターンとなるようにパターニングされる。図6Bは、図6Aの上面図の線A−Aに沿った垂直断面図である。
好ましくは、第1の相隔たる各フィーチャ154の長さまたは幅は、隣接する第1の相隔たるフィーチャ154間の間隔より大きい。例えば、図8Cに見られるように、第1の相隔たる各フィーチャ154の幅は約3Fであり、隣接する第1の相隔たるフィーチャ間の間隔は約1Fである。
充填材160が存在する場合には、フォトレジストフィーチャ170または170/172を除去した後に充填材160も選択的に除去し、図11Aおよび11Bに見られるように、複数の相隔たる端部156を残すことができる。図11Aは、図11Bの線A−Aに沿った垂直断面図である。
以下、正方形もしくは長方形のフィーチャの代わりに、円形もしくは楕円形のフィーチャを使用する代替の実施形態について説明する。
それぞれの円形フィーチャ254は直径が約3Fあり、6つの隣接する円形フィーチャから約1Fの距離だけ離隔されている(フォトリソグラフィのばらつきや誤差を許容する)。隣接するフィーチャ254の中心間の距離は約4Fである。したがって、架空の正三角形255の辺の長さは、図13に見られるように、約4Fある。
そのようなフィーチャ254を形成するには、まずは直径2Fを持つ第1のフォトレジストフィーチャを形成し、前の実施形態で説明したように、RELACS工程かリフロー工程かサイドウォールスペーサ工程により第1のフォトレジストフィーチャの直径を増大させる。あるいは、最初のパターニングで直径3Fのフォトレジストフィーチャを形成する。次に、第1のフォトレジストフィーチャをマスクとして使用して下位層をパターニングし、下位層にフィーチャ254を形成する。
基板上に形成されるモノリシックな三次元メモリアレイは少なくとも、基板から上に第1の高さに形成される第1のメモリレベルと、第1の高さとは異なる第2の高さに形成される第2のメモリレベルとを備える。そのようなマルチレベルアレイでは、基板の上に3レベル、4レベル、8レベルのメモリレベルを形成でき、実際には何レベルでも形成できる。
前述した教示に鑑みれば本発明の数多くの修正ならびに変形が可能である。したがって、本発明は、添付の特許請求の範囲内で、具体的に説明した内容とは異なるやり方で実施することができる。
Claims (19)
- 半導体デバイスを作成する方法であって、
下位層上に第1のフォトレジスト層を形成するステップと、
前記第1のフォトレジスト層を、前記下位層上に位置する複数の相隔たる第1のフォトレジスト部分である第1のフォトレジストパターンとなるようにパターニングするステップと、
前記第1のフォトレジストパターンをマスクとして使用して前記下位層をエッチングし、前記下位層の複数の第1の相隔たる部分を形成するステップと、
前記第1のフォトレジストパターンを除去するステップと、
前記下位層の複数の第1の相隔たる部分上に第2のフォトレジスト層を形成するステップと、
前記第2のフォトレジスト層を、前記下位層の複数の第1の相隔たる部分の端部を覆う複数の第2のフォトレジスト部分である第2のフォトレジストパターンとなるようにパターニングするステップであって、3つの第2のフォトレジスト部分が前記下位層の第1の相隔たる各部分の3つの端部を覆う正三角形を形成するように、前記複数の第2のフォトレジスト部分が前記下位層の複数の第1の相隔たる部分上に配置され、正三角形の頂点が3つの第2のフォトレジスト部分の中心に位置し、頂点をつなぐ架空の線により正三角形の3辺を形成するステップと、
前記下位層の複数の第1の相隔たる部分の複数の相隔たる端部が残るように、前記第2のフォトレジストパターンをマスクとして使用して前記下位層の複数の第1の相隔たる部分の露出部分をエッチングするステップと、
前記第2のフォトレジストパターンを除去するステップと、
を含む方法。 - 請求項1記載の方法において、
前記下位層は、デバイス層上に位置する少なくとも1つのマスキング層であり、
前記下位層の複数の第1の相隔たる部分は、複数の相隔たるマスキング部分であり、
前記複数の相隔たる端部は、複数の相隔たるエッジマスキング部分であり、
各エッジマスキング部分は、それぞれのマスキング部分より小さいサイズを有し、
前記デバイス層は、半導体デバイスのための1つ以上の半導体層、電極を形成する導電層、および/またはデバイスの半導体もしくは導電部分を絶縁するための絶縁層をなす方法。 - 請求項2記載の方法において、
前記複数のエッジマスキング部分をマスクとして使用して前記デバイス層をエッチングし、複数の柱状デバイスを形成するステップをさらに含み、
前記柱状デバイスは、幅よりも高さのほうが大きい高さと幅とを有する円柱形で垂直に向いたものである方法。 - 請求項3記載の方法において、
前記複数の柱状デバイスは、柱状ダイオードステアリング素子と抵抗切り替え素子とをそれぞれ備える複数の不揮発性メモリセルである方法。 - 請求項3記載の方法において、
前記少なくとも1つのマスキング層は、前記デバイス層上に位置するハードマスク層と、前記ハードマスク層上に位置するアモルファスカーボンパターニング膜と、前記アモルファスカーボンパターニング膜上に位置する反射防止層と、前記反射防止層上に位置するキャップ層とを備える方法。 - 請求項1記載の方法において、
隣接する第1のフォトレジスト部分間の距離を減少させるように、前記下位層の複数の第1の相隔たる部分を形成するステップに先立ち、前記第1のフォトレジスト部分のサイズを増加させるステップと、
隣接する第2のフォトレジスト部分間の距離を減少させるように、前記下位層の複数の第1の相隔たる部分の露出部分をエッチングするステップに先立ち、前記第2のフォトレジスト部分のサイズを増加させるステップと、
をさらに含む方法。 - 請求項6記載の方法において、
前記第1および第2のフォトレジスト部分のサイズを増加させるステップは、リフロー工程かRELACS工程により前記第1および第2のフォトレジスト部分のサイズを増加させることを含む方法。 - 請求項6記載の方法において、
隣接する第1のフォトレジスト部分間の距離は、2Fから1Fまで減少され、
隣接する第2のフォトレジスト部分間の距離は、2Fから1Fまで減少され、
Fは、最小加工寸法である方法。 - 請求項6記載の方法において、
前記第2のフォトレジスト部分のサイズを増加させるステップは、前記下位層の複数の第1の相隔たる部分の端部にわたって前記第2のフォトレジスト部分を延在させることを含む方法。 - 請求項1記載の方法において、
前記第2のフォトレジスト層を形成するステップは、前記下位層の複数の第1の相隔たる部分上に前記第2のフォトレジスト層を形成することと、前記下位層の隣接する第1の相隔たる部分間の間隙を前記第2のフォトレジスト層により充填することとを含む方法。 - 請求項1記載の方法において、
前記下位層の複数の第1の相隔たる部分の上と、前記下位層の複数の第1の相隔たる部分間の間隙とに充填材を形成するステップと、
前記充填材を平坦化して、前記下位層の複数の第1の相隔たる部分の上面を露出するステップと、
前記第2のフォトレジストパターンを除去するステップの後に、前記充填材を選択的に除去するステップと、
をさらに含む方法。 - 請求項11記載の方法において、
前記第2のフォトレジスト層を形成するステップは、前記下位層の複数の第1の相隔たる部分の上と、前記充填材の上とに前記第2のフォトレジスト層を形成することを含み、
前記第2のフォトレジスト層をパターニングするステップは、前記下位層の複数の第1の相隔たる部分の端部を覆いかつ前記充填材の少なくとも一部分を覆う複数の第2のフォトレジスト部分を形成することを含む方法。 - 請求項1記載の方法において、
前記下位層の第1の相隔たる各部分の幅は、前記下位層の隣接する第1の相隔たる部分間の間隔より大きい方法。 - 請求項13記載の方法において、
前記下位層の第1の相隔たる各部分の幅は、3Fであり、
前記下位層の隣接する第1の相隔たる部分間の間隔は、1Fであり、
Fは、最小加工寸法である方法。 - 請求項1記載の方法において、
前記下位層の複数の第1の相隔たる各部分は、円形状であり、
前記下位層の複数の第1の相隔たる部分は、前記下位層の第1の相隔たる各部分が等距離をおく6つの最寄の前記下位層の隣接する第1の相隔たる部分によって取り囲まれ、六角形の頂点が等距離をおく6つの最寄の前記下位層の隣接する第1の相隔たる部分の中心に位置し、頂点をつなぐ架空の線により六角形状の6辺を形成するような六角形状に配置され、
前記複数の相隔たる端部は、前記下位層の複数の第1の相隔たる部分の非正規な楕円形端部をなし、
非正規な楕円形は、円弧が重なり合うことにより形成されたアメリカンフットボール形またはラグビーボール形をなす方法。 - 請求項15記載の方法において、
前記下位層の複数の第1の相隔たる各部分は、3Fの直径を有し、
前記下位層の隣接する第1の相隔たる部分の中心間距離は、4Fであり、
前記下位層の隣接する第1の相隔たる部分は、1Fの距離だけ離隔され、
非正規な楕円形の各端部の小径は、0.7Fであり、
Fは、最小加工寸法である方法。 - 請求項15記載の方法において、
前記下位層の下に複数のワード線を形成するステップと、
前記複数のエッジ部分をマスクとして使用して前記下位層をエッチングし、非正規な楕 円断面形状を有する複数の柱状デバイスを形成するステップと、
前記複数の柱状デバイス上に複数のビット線を形成するステップと、
をさらに含む方法。 - 請求項17記載の方法において、
前記複数のワード線は、第1の方向に延在し、
前記複数のビット線は、第2の方向に延在し、
第1の方向は、第2の方向から60度異なり、
前記複数のワード線は、第1のワード線のセットと第2のワード線のセットからなり、
第1の各ワード線は、2つの第2のワード線間に位置し、
第1の各ワード線は、第2の各ワード線の2倍の柱状デバイスと電気的に接触する方法。 - 請求項1記載の方法において、
前記第1のフォトレジスト層は、第1のポジティブフォトレジスト層であり、
前記第2のフォトレジスト層は、第2のポジティブフォトレジスト層である方法。
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TW201009893A (en) | 2010-03-01 |
US20110171809A1 (en) | 2011-07-14 |
CN102077346A (zh) | 2011-05-25 |
EP2294615A2 (en) | 2011-03-16 |
JP2011527115A (ja) | 2011-10-20 |
TWI500070B (zh) | 2015-09-11 |
CN102077346B (zh) | 2013-05-01 |
US20100219510A1 (en) | 2010-09-02 |
KR20110028525A (ko) | 2011-03-18 |
WO2010002683A2 (en) | 2010-01-07 |
WO2010002683A3 (en) | 2010-03-04 |
US8138010B2 (en) | 2012-03-20 |
KR101487288B1 (ko) | 2015-01-29 |
EP2294615B1 (en) | 2017-01-11 |
US20090323385A1 (en) | 2009-12-31 |
US7935553B2 (en) | 2011-05-03 |
US7732235B2 (en) | 2010-06-08 |
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