JP5335828B2 - 導体トラック配列の製造方法 - Google Patents
導体トラック配列の製造方法 Download PDFInfo
- Publication number
- JP5335828B2 JP5335828B2 JP2011009120A JP2011009120A JP5335828B2 JP 5335828 B2 JP5335828 B2 JP 5335828B2 JP 2011009120 A JP2011009120 A JP 2011009120A JP 2011009120 A JP2011009120 A JP 2011009120A JP 5335828 B2 JP5335828 B2 JP 5335828B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor track
- dielectric
- manufacturing
- conductor
- track
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
2 エッチバリア
3 第2誘電体
4 導体トラック
5A 絶縁層
5 レジスト層
6 空洞
TB キャリアトラック
Claims (8)
- a)基材(1、2、3)の上に支持誘電体(3)を形成し、上記支持誘電体(3)の上に導体トラック(4)を形成すること、
b)導体トラック(4)をマスクとして、その幅(B2)が導体トラック(4)の幅(B1)と比して小さい、キャリアトラック(TB)を上記支持誘電体(3)から形成すること、
c)導体トラック(4)を覆い、導体トラック(4)間の空洞(6)を塞ぐ誘電性のレジスト層(5)を形成すること、および、
d)上記空洞(6)内の導体トラック(4)、キャリアトラック(TB)および基材(1、2、3)の上に絶縁層(5A)を形成することを含み、
上記レジスト層(5)と上記絶縁層(5A)とを不均一なCVD堆積プロセスにより同時に形成することを特徴とする導体トラック配列の製造方法。 - 工程a)において、導体トラック(4)は、サブトラクティブプロセスまたはダマシンプロセスにより形成されることを特徴とする請求項1に記載の製造方法。
- 工程a)において、基材は、第1誘電体(1)と、エッチバリア(2)と、第2誘電体(3)とを有し、異方性エッチングにより露出した第2誘電体(3)をエッチバリア(2)まで除去することを特徴とする請求項1または2に記載の製造方法。
- 工程a)において、基材は、第1誘電体(1)のみであり、露出した第1誘電体(1)は、異方性エッチングにより、規定の深さ(T1)まで除去されることを特徴とする請求項1または2に記載の製造方法。
- 工程b)において、等方性のエッチバックは、セルフアラインにより行われ、導体トラック(4)の下部において、第1誘電体(1)または第2誘電体(3)を小さくすることを特徴とする請求項1から4の何れか1項に記載の製造方法。
- 工程b)において、ウェットエッチングまたは等方性ドライエッチングが行われることを特徴とする請求項5に記載の製造方法。
- レジスト層(5)および絶縁層(5A)のためのSiH4、N2Oによる不均一なCVD堆積プロセスは、SiH4とN2Oとの比がSiH4とN2O=1:5〜1:20であり、圧力は、1〜10Torr(133〜1333Pa)であり、温度が350〜400℃であり、RFパワーが200〜400Wであることを特徴とする請求項1に記載の製造方法。
- レジスト層は、大気下、真空下または電気的に非導電性のガス下で形成されることを特徴とする請求項1から7の何れか1項に記載の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102005039323A DE102005039323B4 (de) | 2005-08-19 | 2005-08-19 | Leitbahnanordnung sowie zugehöriges Herstellungsverfahren |
DE102005039323.3 | 2005-08-19 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006224010A Division JP5085072B2 (ja) | 2005-08-19 | 2006-08-21 | 導体トラック配列 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011129939A JP2011129939A (ja) | 2011-06-30 |
JP5335828B2 true JP5335828B2 (ja) | 2013-11-06 |
Family
ID=37697369
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006224010A Expired - Fee Related JP5085072B2 (ja) | 2005-08-19 | 2006-08-21 | 導体トラック配列 |
JP2011009120A Expired - Fee Related JP5335828B2 (ja) | 2005-08-19 | 2011-01-19 | 導体トラック配列の製造方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006224010A Expired - Fee Related JP5085072B2 (ja) | 2005-08-19 | 2006-08-21 | 導体トラック配列 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20070120263A1 (ja) |
JP (2) | JP5085072B2 (ja) |
CN (1) | CN100521187C (ja) |
DE (1) | DE102005039323B4 (ja) |
TW (1) | TWI324820B (ja) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110217657A1 (en) * | 2010-02-10 | 2011-09-08 | Life Bioscience, Inc. | Methods to fabricate a photoactive substrate suitable for microfabrication |
JP5364743B2 (ja) * | 2011-03-01 | 2013-12-11 | 株式会社東芝 | 半導体装置 |
JP5734757B2 (ja) * | 2011-06-16 | 2015-06-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
CN103165516B (zh) * | 2011-12-08 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | 互连结构的制造方法 |
KR102054264B1 (ko) | 2012-09-21 | 2019-12-10 | 삼성전자주식회사 | 반도체 소자 및 그의 제조 방법 |
KR102037830B1 (ko) | 2013-05-20 | 2019-10-29 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9281211B2 (en) * | 2014-02-10 | 2016-03-08 | International Business Machines Corporation | Nanoscale interconnect structure |
EP3140838B1 (en) | 2014-05-05 | 2021-08-25 | 3D Glass Solutions, Inc. | Inductive device in a photo-definable glass structure |
US9941156B2 (en) | 2015-04-01 | 2018-04-10 | Qualcomm Incorporated | Systems and methods to reduce parasitic capacitance |
US10070533B2 (en) | 2015-09-30 | 2018-09-04 | 3D Glass Solutions, Inc. | Photo-definable glass with integrated electronics and ground plane |
KR20180134868A (ko) | 2016-02-25 | 2018-12-19 | 3디 글래스 솔루션즈 인코포레이티드 | 3d 커패시터 및 커패시터 어레이 제작용 광활성 기재 |
US11161773B2 (en) | 2016-04-08 | 2021-11-02 | 3D Glass Solutions, Inc. | Methods of fabricating photosensitive substrates suitable for optical coupler |
WO2018200804A1 (en) | 2017-04-28 | 2018-11-01 | 3D Glass Solutions, Inc. | Rf circulator |
KR102418671B1 (ko) | 2017-07-07 | 2022-07-12 | 3디 글래스 솔루션즈 인코포레이티드 | 패키지 광활성 유리 기판들에서 rf 시스템을 위한 2d 및 3d 집중 소자 디바이스들 |
KR102492733B1 (ko) | 2017-09-29 | 2023-01-27 | 삼성디스플레이 주식회사 | 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법 |
KR102419713B1 (ko) | 2017-12-15 | 2022-07-13 | 3디 글래스 솔루션즈 인코포레이티드 | 결합 전송 라인 공진 rf 필터 |
KR102600200B1 (ko) | 2018-01-04 | 2023-11-10 | 3디 글래스 솔루션즈 인코포레이티드 | 고효율 rf 회로들을 위한 임피던스 정합 도전성 구조 |
EP3643148A4 (en) | 2018-04-10 | 2021-03-31 | 3D Glass Solutions, Inc. | RF INTEGRATED POWER STATE CAPACITOR |
KR102161984B1 (ko) | 2018-05-29 | 2020-10-07 | 3디 글래스 솔루션즈 인코포레이티드 | 저 삽입 손실 rf 전송 라인 |
US11139582B2 (en) | 2018-09-17 | 2021-10-05 | 3D Glass Solutions, Inc. | High efficiency compact slotted antenna with a ground plane |
JP7257707B2 (ja) | 2018-12-28 | 2023-04-14 | スリーディー グラス ソリューションズ,インク | 環状コンデンサrf、マイクロ波及びmm波システム |
KR102493538B1 (ko) | 2018-12-28 | 2023-02-06 | 3디 글래스 솔루션즈 인코포레이티드 | 광활성 유리 기판들에서 rf, 마이크로파, 및 mm 파 시스템들을 위한 이종 통합 |
CA3135975C (en) | 2019-04-05 | 2022-11-22 | 3D Glass Solutions, Inc. | Glass based empty substrate integrated waveguide devices |
JP7188825B2 (ja) | 2019-04-18 | 2022-12-13 | スリーディー グラス ソリューションズ,インク | 高効率ダイダイシング及びリリース |
US11908617B2 (en) | 2020-04-17 | 2024-02-20 | 3D Glass Solutions, Inc. | Broadband induction |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2247986A (en) * | 1990-09-12 | 1992-03-18 | Marconi Gec Ltd | Reducing interconnection capacitance in integrated circuits |
US5461003A (en) * | 1994-05-27 | 1995-10-24 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
US5955786A (en) * | 1995-06-07 | 1999-09-21 | Advanced Micro Devices, Inc. | Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines |
JP3399173B2 (ja) * | 1995-08-18 | 2003-04-21 | ソニー株式会社 | 半導体集積回路装置 |
US5869379A (en) * | 1997-12-08 | 1999-02-09 | Advanced Micro Devices, Inc. | Method of forming air gap spacer for high performance MOSFETS' |
US5953625A (en) * | 1997-12-15 | 1999-09-14 | Advanced Micro Devices, Inc. | Air voids underneath metal lines to reduce parasitic capacitance |
US6380607B2 (en) * | 1997-12-31 | 2002-04-30 | Lg Semicon Co., Ltd. | Semiconductor device and method for reducing parasitic capacitance between data lines |
US6002150A (en) * | 1998-06-17 | 1999-12-14 | Advanced Micro Devices, Inc. | Compound material T gate structure for devices with gate dielectrics having a high dielectric constant |
JP2000174116A (ja) * | 1998-12-03 | 2000-06-23 | Nec Corp | 半導体装置及びその製造方法 |
US6287951B1 (en) * | 1998-12-07 | 2001-09-11 | Motorola Inc. | Process for forming a combination hardmask and antireflective layer |
TW451402B (en) * | 1999-04-19 | 2001-08-21 | United Microelectronics Corp | Manufacturing method of inter-metal dielectric layer |
FR2803092B1 (fr) * | 1999-12-24 | 2002-11-29 | St Microelectronics Sa | Procede de realisation d'interconnexions metalliques isolees dans des circuits integres |
DE10109877A1 (de) * | 2001-03-01 | 2002-09-19 | Infineon Technologies Ag | Leiterbahnanordnung und Verfahren zur Herstellung einer Leiterbahnanordnung |
DE10109778A1 (de) * | 2001-03-01 | 2002-09-19 | Infineon Technologies Ag | Hohlraumstruktur und Verfahren zum Herstellen einer Hohlraumstruktur |
US6403461B1 (en) * | 2001-07-25 | 2002-06-11 | Chartered Semiconductor Manufacturing Ltd. | Method to reduce capacitance between metal lines |
DE10140754A1 (de) * | 2001-08-20 | 2003-03-27 | Infineon Technologies Ag | Leiterbahnanordnung und Verfahren zum Herstellen einer Leiterbahnanordnung |
CN100372113C (zh) * | 2002-11-15 | 2008-02-27 | 联华电子股份有限公司 | 一种具有空气间隔的集成电路结构及其制作方法 |
JP4052950B2 (ja) * | 2003-01-17 | 2008-02-27 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
-
2005
- 2005-08-19 DE DE102005039323A patent/DE102005039323B4/de not_active Expired - Fee Related
-
2006
- 2006-08-08 TW TW095129121A patent/TWI324820B/zh not_active IP Right Cessation
- 2006-08-18 US US11/506,570 patent/US20070120263A1/en not_active Abandoned
- 2006-08-18 CN CNB2006101110574A patent/CN100521187C/zh not_active Expired - Fee Related
- 2006-08-21 JP JP2006224010A patent/JP5085072B2/ja not_active Expired - Fee Related
-
2011
- 2011-01-19 JP JP2011009120A patent/JP5335828B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20070120263A1 (en) | 2007-05-31 |
JP5085072B2 (ja) | 2012-11-28 |
DE102005039323A1 (de) | 2007-02-22 |
TW200709384A (en) | 2007-03-01 |
TWI324820B (en) | 2010-05-11 |
JP2011129939A (ja) | 2011-06-30 |
CN100521187C (zh) | 2009-07-29 |
DE102005039323B4 (de) | 2009-09-03 |
JP2007088439A (ja) | 2007-04-05 |
CN1945823A (zh) | 2007-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5335828B2 (ja) | 導体トラック配列の製造方法 | |
US7514354B2 (en) | Methods for forming damascene wiring structures having line and plug conductors formed from different materials | |
JP5089575B2 (ja) | 相互接続構造体及びその製造方法 | |
US7671442B2 (en) | Air-gap insulated interconnections | |
US9379055B2 (en) | Semiconductor device and method of manufacturing the same | |
EP2264758B1 (en) | Interconnection structure in semiconductor device | |
US6187672B1 (en) | Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing | |
US7867895B2 (en) | Method of fabricating improved interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric | |
CN100470787C (zh) | 半导体器件及其制造方法 | |
US7037851B2 (en) | Methods for selective integration of airgaps and devices made by such methods | |
JP5558662B2 (ja) | デバイス、方法(mimキャパシタおよびその製造方法) | |
US20080299763A1 (en) | Method for fabricating semiconductor device | |
CN100541760C (zh) | 互连中的气隙的横向分布控制 | |
US7071100B2 (en) | Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process | |
JP2003168738A (ja) | 半導体素子及びその製造方法 | |
TW201727709A (zh) | 具有楔形鑲嵌孔洞之半導體結構及其製造方法 | |
KR20070063499A (ko) | 반도체 장치 및 반도체 장치의 제조 방법 | |
US20050161825A1 (en) | Semiconductor device | |
JP2012038961A (ja) | 半導体装置及び半導体装置の製造方法 | |
US20180130697A1 (en) | Semiconductor devices and methods of manufacturing the same | |
JP4152439B2 (ja) | 互い違いに配列される配線を製造するため窪んだローカル導体を使用する集積回路 | |
JP2009026989A (ja) | 半導体装置及び半導体装置の製造方法 | |
US6927113B1 (en) | Semiconductor component and method of manufacture | |
CN110783259A (zh) | 半导体装置 | |
JP2007294625A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130228 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130305 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130425 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130716 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130731 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5335828 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |