JP5282981B2 - 素子搭載基板の製造方法 - Google Patents
素子搭載基板の製造方法 Download PDFInfo
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- JP5282981B2 JP5282981B2 JP2009546983A JP2009546983A JP5282981B2 JP 5282981 B2 JP5282981 B2 JP 5282981B2 JP 2009546983 A JP2009546983 A JP 2009546983A JP 2009546983 A JP2009546983 A JP 2009546983A JP 5282981 B2 JP5282981 B2 JP 5282981B2
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Description
14 パッド
16 仮止め材
17,17x 仮止め材
20,20x 素子
23x 外部電極
24 接着層
Claims (3)
- 加熱されると粘着力を生じる接着層が形成された素子と、基板とを用意する第1の工程と、
前記基板に前記素子を配置する第2の工程と、
前記基板に前記素子が配置された状態で加熱した後に冷却して、前記素子の前記接着層が前記基板に接着される第3の工程と、
を備え、
前記第2の工程において、
前記素子が配置されるべき前記基板の所定領域の一部分に流動性を有する液状の仮止め材を配置した後、前記素子の前記接着層が空間を設けて前記基板に対向し、かつ前記素子が前記仮止め材に接するように、前記基板に前記素子を配置し、
前記第3の工程において、前記仮止め材が加熱されて消失して、前記素子の前記接着層と前記基板との間の前記空間がなくなって前記素子の前記接着層が前記基板に接し、前記素子の前記接着層が前記基板に接着され、前記仮止め材が配置された、前記基板の所定領域の一部分において、前記素子と前記基板とが接触しない状態になることを特徴とする、素子搭載基板の製造方法。 - 前記仮止め材が消失を開始する温度が、前記接着層に粘着力が生じる温度よりも低いことを特徴とする、請求項1に記載の素子搭載基板の製造方法。
- 前記接着層は、熱硬化性樹脂又は熱可塑性樹脂を主成分とすることを特徴とする請求項1又は2に記載の素子搭載基板の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2009546983A JP5282981B2 (ja) | 2007-12-21 | 2008-10-20 | 素子搭載基板の製造方法 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2007329856 | 2007-12-21 | ||
JP2007329856 | 2007-12-21 | ||
PCT/JP2008/068986 WO2009081648A1 (ja) | 2007-12-21 | 2008-10-20 | 素子搭載基板の製造方法 |
JP2009546983A JP5282981B2 (ja) | 2007-12-21 | 2008-10-20 | 素子搭載基板の製造方法 |
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JPWO2009081648A1 JPWO2009081648A1 (ja) | 2011-05-06 |
JP5282981B2 true JP5282981B2 (ja) | 2013-09-04 |
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JP2009546983A Active JP5282981B2 (ja) | 2007-12-21 | 2008-10-20 | 素子搭載基板の製造方法 |
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JP (1) | JP5282981B2 (ja) |
WO (1) | WO2009081648A1 (ja) |
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EP3276652A3 (de) * | 2015-04-02 | 2018-04-25 | Heraeus Deutschland GmbH & Co. KG | Verfahren zum herstellen einer substratanordnung mit einem klebevorfixiermittel, entsprechende substratanordnung, verfahren zum verbinden eines elektronikbauteils mit einer substratanordnung mit anwendung eines auf dem elektronikbauteil und/oder der substratanordnung aufgebrachten klebevorfixiermittels und mit einer substratanordnung verbundenes elektronikbauteil |
CN107210233B (zh) * | 2015-07-23 | 2021-07-23 | 瑞萨电子株式会社 | 半导体器件及其制造方法 |
Citations (3)
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JPS5636121A (en) * | 1979-08-31 | 1981-04-09 | Matsushita Electric Works Ltd | Method of mounting condenser |
JPS63149864U (ja) * | 1987-03-25 | 1988-10-03 | ||
JPH0888464A (ja) * | 1994-09-20 | 1996-04-02 | Sony Corp | フリップチップ実装方法 |
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2008
- 2008-10-20 WO PCT/JP2008/068986 patent/WO2009081648A1/ja active Application Filing
- 2008-10-20 JP JP2009546983A patent/JP5282981B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5636121A (en) * | 1979-08-31 | 1981-04-09 | Matsushita Electric Works Ltd | Method of mounting condenser |
JPS63149864U (ja) * | 1987-03-25 | 1988-10-03 | ||
JPH0888464A (ja) * | 1994-09-20 | 1996-04-02 | Sony Corp | フリップチップ実装方法 |
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JPWO2009081648A1 (ja) | 2011-05-06 |
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