CN107210233B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN107210233B CN107210233B CN201580073894.XA CN201580073894A CN107210233B CN 107210233 B CN107210233 B CN 107210233B CN 201580073894 A CN201580073894 A CN 201580073894A CN 107210233 B CN107210233 B CN 107210233B
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- layer
- semiconductor device
- semiconductor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 413
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 168
- 239000002904 solvent Substances 0.000 claims description 47
- 238000007789 sealing Methods 0.000 claims description 45
- 238000010438 heat treatment Methods 0.000 claims description 18
- 238000007747 plating Methods 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 6
- 239000007787 solid Substances 0.000 claims description 5
- 241000839426 Chlamydia virus Chp1 Species 0.000 description 149
- JPKJQBJPBRLVTM-OSLIGDBKSA-N (2s)-2-amino-n-[(2s,3r)-3-hydroxy-1-[[(2s)-1-[[(2s)-1-[[(2s)-1-[[(2r)-1-(1h-indol-3-yl)-3-oxopropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxobutan-2-yl]-6-iminohexanamide Chemical compound C([C@H](NC(=O)[C@@H](NC(=O)[C@@H](N)CCCC=N)[C@H](O)C)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@H](CC=1C2=CC=CC=C2NC=1)C=O)C1=CC=CC=C1 JPKJQBJPBRLVTM-OSLIGDBKSA-N 0.000 description 124
- 102100031277 Calcineurin B homologous protein 1 Human genes 0.000 description 124
- 101000777252 Homo sapiens Calcineurin B homologous protein 1 Proteins 0.000 description 124
- 101000943802 Homo sapiens Cysteine and histidine-rich domain-containing protein 1 Proteins 0.000 description 124
- 241001510512 Chlamydia phage 2 Species 0.000 description 54
- 102100031272 Calcineurin B homologous protein 2 Human genes 0.000 description 52
- 101000777239 Homo sapiens Calcineurin B homologous protein 2 Proteins 0.000 description 52
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 43
- 229910052709 silver Inorganic materials 0.000 description 40
- 239000004332 silver Substances 0.000 description 40
- 230000004048 modification Effects 0.000 description 26
- 238000012986 modification Methods 0.000 description 26
- 239000000853 adhesive Substances 0.000 description 19
- 230000001070 adhesive effect Effects 0.000 description 19
- 230000006872 improvement Effects 0.000 description 17
- 239000002245 particle Substances 0.000 description 17
- 239000011347 resin Substances 0.000 description 17
- 229920005989 resin Polymers 0.000 description 17
- 230000008569 process Effects 0.000 description 16
- 229960005552 PAC-1 Drugs 0.000 description 15
- YQNRVGJCPCNMKT-JLPGSUDCSA-N 2-(4-benzylpiperazin-1-yl)-n-[(2-hydroxy-3-prop-2-enyl-phenyl)methylideneamino]acetamide Chemical compound OC1=C(CC=C)C=CC=C1\C=N/NC(=O)CN1CCN(CC=2C=CC=CC=2)CC1 YQNRVGJCPCNMKT-JLPGSUDCSA-N 0.000 description 14
- 102100021786 CMP-N-acetylneuraminate-poly-alpha-2,8-sialyltransferase Human genes 0.000 description 14
- 101000616698 Homo sapiens CMP-N-acetylneuraminate-poly-alpha-2,8-sialyltransferase Proteins 0.000 description 14
- 101001139126 Homo sapiens Krueppel-like factor 6 Proteins 0.000 description 14
- 101001133600 Homo sapiens Pituitary adenylate cyclase-activating polypeptide type I receptor Proteins 0.000 description 14
- 101001080401 Homo sapiens Proteasome assembly chaperone 1 Proteins 0.000 description 14
- 102100020679 Krueppel-like factor 6 Human genes 0.000 description 14
- 238000005245 sintering Methods 0.000 description 12
- FQVLRGLGWNWPSS-BXBUPLCLSA-N (4r,7s,10s,13s,16r)-16-acetamido-13-(1h-imidazol-5-ylmethyl)-10-methyl-6,9,12,15-tetraoxo-7-propan-2-yl-1,2-dithia-5,8,11,14-tetrazacycloheptadecane-4-carboxamide Chemical compound N1C(=O)[C@@H](NC(C)=O)CSSC[C@@H](C(N)=O)NC(=O)[C@H](C(C)C)NC(=O)[C@H](C)NC(=O)[C@@H]1CC1=CN=CN1 FQVLRGLGWNWPSS-BXBUPLCLSA-N 0.000 description 11
- 238000001514 detection method Methods 0.000 description 11
- 102100034035 Alcohol dehydrogenase 1A Human genes 0.000 description 9
- 101000892220 Geobacillus thermodenitrificans (strain NG80-2) Long-chain-alcohol dehydrogenase 1 Proteins 0.000 description 9
- 101000780443 Homo sapiens Alcohol dehydrogenase 1A Proteins 0.000 description 9
- 238000003825 pressing Methods 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 102100034044 All-trans-retinol dehydrogenase [NAD(+)] ADH1B Human genes 0.000 description 6
- 101710193111 All-trans-retinol dehydrogenase [NAD(+)] ADH4 Proteins 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000001035 drying Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000000470 constituent Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 238000011835 investigation Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 101000832889 Scheffersomyces stipitis (strain ATCC 58785 / CBS 6054 / NBRC 10063 / NRRL Y-11545) Alcohol dehydrogenase 2 Proteins 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- YQNRVGJCPCNMKT-LFVJCYFKSA-N 2-[(e)-[[2-(4-benzylpiperazin-1-ium-1-yl)acetyl]hydrazinylidene]methyl]-6-prop-2-enylphenolate Chemical compound [O-]C1=C(CC=C)C=CC=C1\C=N\NC(=O)C[NH+]1CCN(CC=2C=CC=CC=2)CC1 YQNRVGJCPCNMKT-LFVJCYFKSA-N 0.000 description 1
- 101100462537 Caenorhabditis elegans pac-1 gene Proteins 0.000 description 1
- 101100148606 Caenorhabditis elegans pst-1 gene Proteins 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 101100117764 Mus musculus Dusp2 gene Proteins 0.000 description 1
- 101000928111 Scheffersomyces stipitis (strain ATCC 58785 / CBS 6054 / NBRC 10063 / NRRL Y-11545) Alcohol dehydrogenase 1 Proteins 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000011345 viscous material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/278—Post-treatment of the layer connector
- H01L2224/27848—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
- H01L2224/37599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/404—Connecting portions
- H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
- H01L2224/40499—Material of the auxiliary connecting means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73263—Layer and strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83439—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
- H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84399—Material
- H01L2224/84498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/84499—Material of the matrix
- H01L2224/84594—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/845 - H01L2224/84591
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84399—Material
- H01L2224/84498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/84598—Fillers
- H01L2224/84599—Base material
- H01L2224/846—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/84638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/84639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1425—Converter
- H01L2924/14252—Voltage converter
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明提供半导体器件及其制造方法,提高半导体器件的可靠性。因此,将尽可能不在成为多孔质状态的Ag层(AGL)的表面上形成临时固定材料(TA),同时,使用具有粘性的临时固定材料(TA)将搭载于Ag层(AGL)上的半导体芯片(CHP1)固定这一基本思想具体化。具体来说,以具有与芯片搭载部(TAB)接触的部分的方式供给临时固定材料(TA),且以半导体芯片(CHP1)的背面的一部分与临时固定材料(TA)接触的方式将半导体芯片(CHP1)搭载于Ag层(AGL)上。
Description
技术领域
本发明涉及半导体器件及其制造技术,例如,涉及适用于将芯片搭载部和半导体芯片经由Ag层(银层)电连接的半导体器件及其制造技术的有效技术。
背景技术
日本特开2011-249801号公报(专利文献1)中记载有通过向烧结层的表面供给液体,使烧结层与功率半导体元件的粘接力提高来固定的技术。
现有技术文献
专利文献
专利文献1:日本特开2011-249801号公报
发明内容
目前,作为将芯片搭载部和半导体芯片进行连接的材料,使用含有铅且具有约300℃左右的熔点的所谓高熔点焊锡材料。但是,从对环境的考虑出发,正在发展向不含铅的无铅材料的转换。在这样的潮流中,着眼于电阻率低的银(Ag)材料,通过Ag层将芯片搭载部和半导体芯片电连接。在此,作为将芯片搭载部和半导体芯片进行连接的Ag层,通常使用具有夹着环氧树脂等使银颗粒彼此接合的构造的Ag层,但近年来,几乎不含环氧树脂等而通过施加热量和压力来形成银颗粒彼此的金属结合的构造(即被称作烧结银)的Ag层备受关注。根据该烧结构造的Ag层,具有能够降低Ag层的电阻率、并且能够提高热传导率的优点。
本说明书中所说的Ag层以通过施加热量和压力而形成银颗粒彼此的金属结合的烧结构造的Ag层为前提。该烧结构造的Ag层通过以下所示的工序形成。即,例如,通过将溶剂中含有银颗粒的膏向芯片搭载部上供给(印刷)并进行加热,从该膏中使溶剂挥发来进行干燥。由此,在形成了Ag层后,在该Ag层上搭载半导体芯片,然后,经由半导体芯片对Ag层施加热量和压力,由此,形成形成了银颗粒彼此的金属结合的烧结构造的Ag层。
在此,通过实施加热处理,从膏中使溶剂挥发而使膏干燥的工序,是为了抑制在Ag层上搭载了半导体芯片后Ag层中残存的溶剂挥发而导致在半导体芯片和Ag层之间产生空隙的情况而实施的。但是,在该干燥工序中,由于溶剂成分从膏挥发,所以干燥了的Ag层成为多孔质状态,膏所具有的粘性(粘着性)也消失。当在该状态下在Ag层上搭载半导体芯片时,由于Ag层不存在粘性,所以不能可靠地固定半导体芯片,半导体芯片容易产生错位。本发明人新发现:当产生这种错位时,在隔着半导体芯片对Ag层施加热量和压力的工序中,在半导体芯片上局部施加大的压力,由此,半导体芯片上产生裂纹的可能性变高。即,根据本发明人的探讨,在芯片搭载部和半导体芯片的电连接采用烧结构造的Ag层的情况下,从提高半导体器件的可靠性的观点出发,存在改善的余地。
其它课题和新的特征将根据本说明书的记述及附图变得明朗。
一实施方式的半导体器件的制造方法具有将半导体芯片搭载于芯片搭载部上的第一Ag层上的工序。而且,在该工序中,在以与芯片搭载部接触的方式供给了第一材料后,以使半导体芯片的背面的一部分与第一材料接触的方式将半导体芯片搭载于第一Ag层上。
发明效果
根据一实施方式,能够提高半导体器件的可靠性。
附图说明
图1的(a)~(e)是示意性表示在关联技术中,通过使用烧结构造的Ag层而实现芯片搭载部与半导体芯片的电连接的半导体器件的制造工序的一部分的图。
图2的(a)~(b)是说明使用临时固定材料的技术中的改善的余地的图。
图3的(a)~(b)是说明使用临时固定材料的技术中的改善的余地的图。
图4的(a)是表示实施方式的半导体器件的外观结构的俯视图,(b)是侧视图,(c)是仰视图。
图5是表示实施方式的半导体器件的封固体的内部构造的图,(a)是俯视图,(b)是(a)的A-A线的剖视图,(c)是(a)的B-B线的剖视图。
图6是放大示出在实施方式的半导体器件中芯片搭载部和半导体芯片的连接构造的示意图。
图7是放大示出在探讨例中芯片搭载部和半导体芯片的连接构造的示意图。
图8是表示实施方式的半导体器件的制造工序的流程的流程图。
图9是表示实施方式的半导体器件的制造工序的图,(a)是俯视图,(b)是剖视图。
图10是表示接着图9的半导体器件的制造工序的图,(a)是俯视图,(b)是剖视图。
图11是表示接着图10的半导体器件的制造工序的图,(a)是俯视图,(b)是剖视图。
图12是表示接着图11的半导体器件的制造工序的图,(a)是俯视图,(b)是剖视图。
图13是表示接着图12的半导体器件的制造工序的图,(a)是俯视图,(b)是剖视图。
图14是表示接着图13的半导体器件的制造工序的图,(a)是俯视图,(b)是剖视图。
图15是表示接着图14的半导体器件的制造工序的图,(a)是俯视图,(b)是剖视图。
图16是表示接着图15的半导体器件的制造工序的图,(a)是俯视图,(b)是剖视图。
图17是表示接着图16的半导体器件的制造工序的图,(a)是俯视图,(b)是剖视图。
图18的(a)是示意性表示利用形成于芯片搭载部上的临时固定材料来固定半导体芯片的状态的放大俯视图,(b)是(a)的A-A线的剖视图。
图19是示意性表示模塑工序后的状态的剖视图。
图20的(a)是示意性表示在变形例1中利用形成于芯片搭载部上的临时固定材料来固定半导体芯片的状态的放大俯视图,(b)是(a)的A-A线的剖视图。
图21的(a)是示意性表示在变形例2中利用形成于芯片搭载部上的临时固定材料固定半导体芯片的状态的放大俯视图,(b)是(a)的A-A线的剖视图。
具体实施方式
在以下的实施方式中,为了便于说明,在需要时分割成多个部分或实施方式来进行说明,除特别明示的情况以外,它们并非相互无关,而一方为另一方的一部分或全部的变形例、详细内容、补充说明等的关系。
另外,在以下的实施方式中,在提及要素的数量等(包含个数、数值、量、范围等)的情况下,除特别明示的情况以及原理上明显限于特定的数量的情况以外,不限于该特定的数量,可以是特定的数量以上或以下。
进而,在以下的实施方式中,对于其构成要素(也包括要素步骤等),除特别明示的情况以及原理上明显认为是必须的情况等以外,当然并非一定是必须的。
同样地,在以下的实施方式中,当提及构成要素等的形状、位置关系等时,除特别明示的情况以及原理上明显认为并非如此的情况等以外,实质上包含近似或类似于该形状等的形状、位置关系等。这对上述数值和范围也是同样的。
另外,在用于说明实施方式的全部附图中,原则上对同一部件赋予同一附图标记,并省略对其重复说明。此外,为了容易理解附图,有时即使是俯视图,也赋予影线。
<烧结构造的Ag层的定义>
首先,开始对与本说明书中作为前提的烧结构造的Ag层有关的定义进行说明。本说明书中作为前提的烧结构造的Ag层在以下方面与含有环氧树脂作为粘合剂的Ag层不同。即,介有环氧树脂的构造的Ag层和烧结构造的Ag层均以膏状态被供给,但用于形成介有环氧树脂的构造的Ag层的膏中,树脂成分相对于银(1)的体积比为0.7左右。与之相对,用于形成在本说明书中作为对象的烧结构造的Ag层的膏中,树脂成分相对于银(1)的体积比为0.3左右。而且,在将膏固化后,介有环氧树脂的构造的Ag层中,树脂成分相对于银(1)的体积比为0.5左右,与之相对,在将膏固化后,在烧结构造的Ag层中,树脂成分几乎不存在。像这样,定义了本说明书中作为对象的烧结构造的Ag层。
<改善的探讨>
接着,以芯片搭载部和半导体芯片的电连接采用烧结构造的Ag层为前提,本发明人从提高半导体器件的可靠性的观点出发进行了改善的探讨,结果了解到尚存在改善的余地。因此,以下,在对该改善的余地进行了说明之后,说明对该改善的余地进行了研究的本实施方式的技术思想。
图1的(a)~(e)是示意性表示在关联技术中,通过使用烧结构造的Ag层而实现芯片搭载部和半导体芯片的电连接的半导体器件的制造工序的一部分的图。此外,本说明书中所说的“关联技术”是具有发明人新发现的课题的技术。进而,本说明书中所说的“关联技术”不是公知的现有技术,而是意图上记载新的技术思想的前提技术(非公知技术)的技术。
首先,如图1的(a)所示,例如,通过使用印刷法,在芯片焊盘(芯片搭载部)DP上涂敷含有银颗粒和溶剂的膏PST1。之后,如图1的(b)所示,将芯片焊盘DP配置于加热板HPLT上进行加热,由此,使涂敷于芯片焊盘DP上的膏PST1中所含的溶剂挥发,使膏PST1干燥。由此,在芯片焊盘DP上形成多孔质状态的Ag层AGL。
接着,如图1的(c)所示,使芯片焊盘DP从加热板HPLT上移动到安装载台MS上后,在Ag层AGL上搭载半导体芯片CHP。然后,在Ag层AGL上搭载了半导体芯片CHP的状态下,使芯片焊盘DP从安装载台MS移动到输送轨道RAL上。此时,例如有时有振动作用在芯片焊盘DP上,且存在于半导体芯片CHP的下层的Ag层AGL在多孔质状态下不具有粘性(粘着性),因此,如图1的(d)所示,极小的外扰就容易使半导体芯片CHP引起错位。然后,在该情况下,如图1的(e)所示,在半导体芯片CHP与本来的搭载位置错开的状态下,对于搭载有半导体芯片CHP的芯片焊盘DP,利用夹设有缓冲材料CS的压头PH实施加热处理及加压处理。由此,对Ag层AGL施加压力,形成烧结构造的Ag层AGL(SIN),但与此同时,如图1的(e)所示,对产生了错位的半导体芯片CHP局部施加力,半导体芯片CHP上可能会产生裂纹。因此,作为关联技术,从提高半导体器件的可靠性的观点出发,存在改善的余地。
在此,作为消除上述的改善余地的技术,能够考虑以下所示的技术。例如,如图2的(a)所示,考虑向干燥而成为多孔质状态的Ag层AGL的表面供给由液体构成的临时固定材料TA。该情况下,由液体构成的临时固定材料TA具有粘性,因此,在供给了该临时固定材料TA的Ag层AGL上搭载半导体芯片时,通过临时固定材料TA所具有的粘性来固定半导体芯片。其结果为,认为能够抑制半导体芯片的错位。
但是,如图2的(b)所示,Ag层AGL为多孔质状态,向Ag层AGL上供给的临时固定材料TA容易浸入多孔质状态的Ag层AGL中。这意味着残存于Ag层AGL的表面上的临时固定材料TA的量发生变化。即,在该技术中,如图3的(a)所示,有助于保持半导体芯片CHP的位置的临时固定材料TA的量不稳定,由此,即使向Ag层AGL上供给临时固定材料TA,也不能有效抑制半导体芯片CHP的错位。进而,如图3的(b)所示,当使用压头PH对Ag层AGL实施加热处理及加压处理时,浸入到Ag层AGL的临时固定材料TA挥发,但由于挥发的溶剂没有泄漏路径而被半导体芯片CHP的下层俘获,所以在半导体芯片CHP的下层的Ag层AGL(SIN)产生空隙VD。其结果为,因空隙VD而可能在半导体芯片CHP和Ag层AGL(SIN)之间产生剥离,或者在半导体芯片CHP上产生裂纹。
如上,在上述的技术中,不仅无法有效抑制半导体芯片CHP的错位,而且还在半导体芯片CHP和Ag层AGL(SIN)之间招致空隙VD的产生,认为无法实现半导体器件的可靠性提高。
因此,在本实施方式中,从防止半导体芯片CHP的错位的观点出发,实施了研究,以下,参照附图说明实施了该研究的本实施方式的技术思想。
<实施方式的半导体器件的安装结构>
本实施方式的半导体器件例如与逆变器电路有关,将成为逆变器电路的构成要素的一个绝缘栅双极型晶体管(以下为IGBT)和一个二极管作为一个封装。即,例如,通过使用6个本实施方式的半导体器件,构成成为驱动3相电机的3相逆变器电路的电子装置(功率模块)。
图4是表示本实施方式的半导体器件PAC1的外观结构的图。具体来说,图4的(a)是表示本实施方式的半导体器件PAC1的外观结构的俯视图,图4的(b)是侧视图,图4的(c)是仰视图。
如图4的(a)所示,本实施方式的半导体器件PAC1具有形成矩形形状的由树脂构成的封固体MR。该封固体MR具有图4的(a)所示的上表面、与该上表面相反侧的下表面(图4的(c))、在厚度方向上位于上表面和下表面之间的第一侧面及与第一侧面相对的第二侧面。图4的(a)中,图示构成第一侧面的边S1,且图示构成第二侧面的边S2。进而,封固体MR具有与第一侧面及第二侧面交叉的第三侧面、和与第一侧面及第二侧面交叉且与第三侧面相对的第四侧面。图4的(a)中,图示构成第三侧面的边S3,并且图示构成第四侧面的边S4。
在此,在本实施方式的半导体器件PAC1中,如图4的(a)所示,从第一侧面突出多个引线LD1各自的一部分,且从第二侧面突出多个引线LD2各自的一部分。此时,引线LD1构成发射极端子ET,引线LD2构成信号端子SGT。而且,构成发射极端子ET的多个引线LD1各自的宽度比构成信号端子SGT的多个引线LD2各自的宽度大。换言之,在本实施方式中,在将多个引线LD1统称为第一引线(第一引线组),将多个引线LD2统称为第二引线(第二引线组)的情况下,从第一引线的封固体MR露出的部分由多个部分(多个引线LD1)构成,且从第二引线的封固体MR露出的部分由多个部分(多个引线LD2)构成。此时,俯视时,第一引线的多个部分各自的宽度也能够比多个引线LD2各自的宽度宽。这是考虑到,由于在发射极端子ET流通大电流,所以需要尽量降低电阻,与之相对,在信号端子SGT仅流通微小的电流。
接着,如图4的(b)所示,在本实施方式的半导体器件PAC1中,将从封固体MR突出的引线LD1及引线LD2折弯加工成鸥翼状。由此,半导体器件PAC1的安装容易性提高。进而,如图4的(c)所示,在本实施方式的半导体器件PAC1中,从封固体MR的下表面(背面)露出芯片搭载部TAB的下表面(背面)。由此,能够提高半导体器件的散热效率。
接着,对构成本实施方式的半导体器件PAC1的封固体MR的内部构造进行说明。图5是表示本实施方式中的半导体器件PAC1的封固体MR的内部构造的图,图5的(a)与俯视图对应,图5的(b)与图5的(a)的A-A线的剖视图对应,图5的(c)与图5的(a)的B-B线的剖视图对应。
首先,在图5的(a)中,在封固体MR的内部配置有矩形形状的芯片搭载部(芯片焊盘)TAB。该芯片搭载部TAB也作为用于提高散热效率的散热片起作用,例如,由以热传导率高的铜为主成分的材料构成。在此,“主成分”是指构成部件的构成材料中、最多含有的材料成分,例如,“以铜为主成分的材料”是指部件的材料中含有铜最多。本说明书中使用“主成分”这一术语的意图例如用于表现部件基本上由铜构成,但不排除还含有杂质的情况。
在芯片搭载部TAB上,例如隔着由烧结构造的Ag层构成的导电性粘接材料ADH1搭载有形成有IGBT的半导体芯片CHP1、及形成有二极管的半导体芯片CHP2。此时,将搭载有半导体芯片CHP1及半导体芯片CHP2的面定义为芯片搭载部TAB的上表面,将与该上表面相反侧的面定义为下表面。该情况下,半导体芯片CHP1及半导体芯片CHP2搭载于芯片搭载部TAB的上表面上。特别是,形成有二极管的半导体芯片CHP2以形成于半导体芯片CHP2的背面的阴极电极焊盘经由导电性粘接材料ADH1与芯片搭载部TAB的上表面接触的方式配置。该情况下,形成于半导体芯片CHP2的表面的阳极电极焊盘ADP朝上。另一方面,形成有IGBT的半导体芯片CHP1以形成于半导体芯片CHP1的背面的集电极(集电极焊盘)经由导电性粘接材料ADH1与芯片搭载部TAB的上表面接触的方式配置。该情况下,形成于半导体芯片CHP1的表面的发射极焊盘EP及多个电极焊盘朝上。因此,半导体芯片CHP1的集电极焊盘和半导体芯片CHP2的阴极电极焊盘经由芯片搭载部TAB电连接。
接着,如图5的(a)所示,在半导体芯片CHP1的发射极焊盘EP、及半导体芯片CHP2的阳极电极焊盘ADP上,例如隔着由烧结构造的Ag层构成的导电性粘接材料ADH2配置有作为导电性部件的夹片CLP。而且,该夹片CLP经由导电性粘接材料ADH2与发射极端子ET连接。因此,半导体芯片CHP1的发射极焊盘EP和半导体芯片CHP2的阳极电极焊盘ADP经由夹片CLP与发射极端子ET电连接。即,在本实施方式中,夹片CLP经由由多个Ag的薄片形成的烧结构造的Ag层与半导体芯片CHP的发射极焊盘EP和发射极端子ET(引线LD1)电连接。该夹片CLP例如由以铜为主成分的板状部件构成。即,在本实施方式中,从半导体芯片CHP1的发射极焊盘EP直至发射极端子ET流通大电流,因此,使用能够确保大的面积的夹片CLP,以能够流通大电流。
另外,如图5的(a)所示,在半导体芯片CHP1的表面形成有多个电极焊盘,该多个电极焊盘分别通过作为导电性部件的导线W与信号端子SGT电连接。具体来说,多个电极焊盘包含栅电极焊盘GP、温度探测用电极焊盘TCP、温度探测用电极焊盘TAP、电流探测用电极焊盘SEP、开尔文探测用电极焊盘KP。而且,栅电极焊盘GP通过导线W与作为信号端子SGT之一的栅极端子GT电连接。同样地,温度探测用电极焊盘TCP通过导线W与作为信号端子SGT之一的温度探测用端子TCT电连接,温度探测用电极焊盘TAP通过导线W与作为信号端子SGT之一的温度探测用端子TAT电连接。另外,电流探测用电极焊盘SEP通过导线W与作为信号端子SGT之一的电流探测用端子SET电连接,开尔文探测用电极焊盘KP通过导线W与开尔文端子KT电连接。此时,导线W例如由以金、铜或铝为主成分的导电性部件构成。
在此,如图5的(a)所示,俯视时,半导体芯片CHP2以位于发射极端子ET和半导体芯片CHP1之间的方式搭载于芯片搭载部TAB的上表面上,且半导体芯片CHP1以位于半导体芯片CHP2和信号端子SGT之间的方式搭载于芯片搭载部TAB的上表面上。
换言之,发射极端子ET、半导体芯片CHP2、半导体芯片CHP1及信号端子SGT沿着作为第一方向的y方向配置。具体来说,俯视时,半导体芯片CHP2以比半导体芯片CHP1更接近发射极端子ET的方式搭载于芯片搭载部TAB的上表面上,且半导体芯片CHP1以比半导体芯片CHP2更接近信号端子SGT的方式搭载于芯片搭载部TAB的上表面上。
而且,俯视时,以栅电极焊盘GP比发射极焊盘EP更接近信号端子SGT的方式将半导体芯片CHP1搭载于芯片搭载部TAB的上表面上。进而换言之,俯视时,以包含栅电极焊盘GP、温度探测用电极焊盘TCP、温度探测用电极焊盘TAP、电流探测用电极焊盘SEP、开尔文探测用电极焊盘KP在内的多个电极焊盘比发射极焊盘EP更接近信号端子SGT的方式将半导体芯片CHP1搭载于芯片搭载部TAB的上表面上。换言之,半导体芯片CHP1的多个电极焊盘在俯视时,也能够沿着半导体芯片CHP1的边中的最接近信号端子SGT的边配置。此时,如图5的(a)所示,俯视时,夹片CLP以不与包含栅电极焊盘GP在内的多个电极焊盘及多个导线W的任一个重合的方式配置。
在这样内部构成的半导体器件PAC1中,将半导体芯片CHP1、半导体芯片CHP2、芯片搭载部TAB的一部分、发射极端子ET的一部分、多个信号端子SGT各自的一部分、夹片CLP及导线W例如通过树脂封固,由此构成封固体MR。
接着,在图5的(c)中,在芯片搭载部TAB的上表面上,隔着由烧结构造的Ag层构成的导电性粘接材料ADH1搭载有形成有IGBT的半导体芯片CHP1、和形成有二极管的半导体芯片CHP2。而且,在从半导体芯片CHP1的表面上直至半导体芯片CHP2的表面上,隔着由烧结构造的Ag层构成的导电性粘接材料ADH2配置有夹片CLP。该夹片CLP进一步通过导电性粘接材料ADH2与发射极端子ET连接,发射极端子ET的一部分从封固体MR露出。另外,半导体芯片CHP1通过导线W与配置于发射极端子ET(引线LD1)相反侧的信号端子SGT连接,信号端子SGT(引线LD2)的一部分也从封固体MR露出。
在此,如图5的(b)所示,芯片搭载部TAB的下表面从封固体MR的下表面露出,该露出的芯片搭载部TAB的下表面成为集电极端子。而且,芯片搭载部TAB的下表面在将半导体器件PAC1安装于布线基板上时成为能够与形成于布线基板上的布线焊接的面。
在芯片搭载部TAB的上表面上搭载有半导体芯片CHP1和半导体芯片CHP2,半导体芯片CHP1的集电极焊盘和半导体芯片CHP2的阴极电极焊盘经由由烧结构造的Ag层构成的导电性粘接材料ADH1与芯片搭载部TAB接触。因此,集电极焊盘和阴极电极焊盘经由芯片搭载部TAB电连接,结果是与集电极端子电连接。进而,如图5的(c)所示,芯片搭载部TAB的厚度比发射极端子ET或信号端子SGT的厚度厚。
在本实施方式的半导体器件中,导电性粘接材料ADH1及导电性粘接材料ADH2由烧结构造的Ag层构成。该烧结构造的Ag层是成分中不含铅的无铅材料,因此,具有在环境上优异的优点。另外,烧结构造的Ag层在温度循环性或功率循环性上优异,得到能够提高半导体器件PAC1的可靠性的优点。
基本上,在本实施方式的半导体器件PAC1中,假设导电性粘接材料ADH1和导电性粘接材料ADH2为相同的材料成分。但不限于此,例如,构成导电性粘接材料ADH1的材料和构成导电性粘接材料ADH2的材料也可以由不同的材料成分构成。例如,在本实施方式中,构成导电性粘接材料ADH1的烧结构造的Ag层被实施加压处理。另一方面,构成导电性粘接材料ADH1的烧结构造的Ag层未被实施加压处理。
本实施方式的半导体器件如上述那样安装构成。即,本实施方式中的半导体器件PAC1具有:半导体芯片CHP1,其具有形成有发射极焊盘EP的表面、和与表面相反侧的面即形成有集电极的背面;以及芯片搭载部TAB,其具有搭载有半导体芯片CHP1的上表面、和与上表面相反侧的面即下表面。进而,半导体器件PAC1具有经由夹片CLP与半导体芯片CHP1的发射极焊盘EP电连接的引线LD1、和将半导体芯片CHP1与夹片CLP树脂封固的封固体MR。此时,半导体芯片CHP1的集电极经由由多个Ag的薄片形成的烧结构造的Ag层(导电性粘接材料ADH1)与芯片搭载部TAB的上表面电连接。
<实施方式中的半导体器件的构造上的特征>
接着,说明本实施方式的半导体器件的构造上的特征点。
图6是放大示出在本实施方式的半导体器件中芯片搭载部TAB和半导体芯片CHP1的连接构造的示意图。图6中,例如在由铜材构成的芯片搭载部TAB的上表面上形成有通过镀敷法形成的银膜AGF。另一方面,在半导体芯片CHP1的背面形成有通过镀敷法形成的金膜AUF,在形成于芯片搭载部TAB的上表面的银膜AGF和形成于半导体芯片CHP1的背面的金膜AUF之间形成有烧结构造的Ag层AGL(SIN)。因此,形成于芯片搭载部TAB的上表面上的银膜AGF与烧结构造的Ag层AGL(SIN)电连接。
对被夹持在形成于芯片搭载部TAB的上表面的银膜AGF和形成于半导体芯片CHP1的背面的金膜AUF之间的烧结构造的Ag层AGL(SIN)实施如后述的制造工序中所说明的加热处理及加压处理。然后,如图6所示,该加压处理的结果是烧结构造的Ag层AGL(SIN)的一部分从半导体芯片CHP1的端部溢出。进而,在本实施方式的半导体器件中,在半导体芯片CHP1的外侧也形成有无加压状态的Ag层AGL。即,由于加压处理是经由半导体芯片CHP1实施的,所以对形成于半导体芯片CHP1的外侧的Ag层AGL未施加加压处理,因此成为无加压状态的Ag层AGL。因此,在本实施方式中,在从半导体芯片CHP1的表面俯视时,在与半导体芯片CHP1重合的部分形成的由经加压的烧结构造构成的Ag层AGL(SIN)的银的密度能够比在不与半导体芯片CHP1重合的部分形成的由无加压的烧结构造构成的Ag层AGL的银的密度高。另一方面,在与半导体芯片CHP1重合的部分形成的由经加压的烧结构造构成的Ag层AGL(SIN)的银的密度比在芯片搭载部TAB的上表面上形成的银膜AGF的密度低。换言之,在芯片搭载部TAB的上表面上形成的银膜AGF的密度比在与半导体芯片CHP1重合的部分形成的由经加压的烧结构造构成的Ag层AGL(SIN)的银的密度高。
然后,如图6所示,由经加压的烧结构造构成的Ag层AGL(SIN)形成为被芯片搭载部TAB和半导体芯片CHP1夹持,由无加压的烧结构造构成的Ag层AGL在芯片搭载部TAB的上表面上直至半导体芯片CHP1的侧面地形成。因此,由无加压的烧结构造构成的Ag层AGL具有厚度比由经加压的烧结构造构成的Ag层AGL(SIN)更厚的部分。然后,如图6所示,以覆盖由无加压的烧结构造构成的Ag层AGL的方式形成由树脂构成的封固体MR。
如上,本实施方式的特征点在于,在被芯片搭载部TAB和半导体芯片CHP1夹持的区域形成有由经加压的烧结构造构成的Ag层AGL(SIN),另一方面,在从芯片搭载部TAB的上表面上直至半导体芯片CHP1的端部侧面形成有由无加压的烧结构造构成的Ag层AGL。
根据这样构成的本实施方式的半导体器件,能够获得以下所示的优点。以下,具体来说,一边与探讨例的半导体器件进行对比,一边说明本实施方式的半导体器件的优点。
图7是放大示出在探讨例中芯片搭载部TAB和半导体芯片CHP1的连接构造的示意图。如参照图6及图7可知,探讨例和本实施方式的不同点在于,在探讨例中,在从芯片搭载部TAB的上表面上直至半导体芯片CHP的端部侧面未形成有由无加压的烧结构造构成的Ag层AGL。即,在本实施方式中,以比半导体芯片CHP1的平面面积大的面积形成烧结构造的Ag层。其结果,如图6所示,在被芯片搭载部TAB和半导体芯片CHP夹持的区域形成有由经加压的烧结构造构成的Ag层AGL(SIN),并且在从芯片搭载部TAB的上表面上直至半导体芯片CHP的端部侧面形成有由无加压的烧结构造构成的Ag层AGL。与之相对,在探讨例中,以与半导体芯片CHP1的平面积同等程度的面积形成烧结构造的Ag层。其结果,如图7所示,在被芯片搭载部TAB和半导体芯片CHP1夹持的区域形成由经加压的烧结构造构成的Ag层AGL(SIN),另一方面,在从芯片搭载部TAB的上表面上直至半导体芯片CHP的端部侧面未形成有由无加压的烧结构造构成的Ag层。
在这样构成的探讨例中,存在以下所示的改善的余地。即,在探讨例中,在从芯片搭载部TAB的上表面上直至半导体芯片CHP的端部侧面未形成有由无加压的烧结构造构成的Ag层。因此,如图7所示,形成于芯片搭载部TAB的上表面上的银膜AGF和由树脂构成的封固体MR直接接触。在此,由于通过镀敷法形成的银膜AGF和由树脂构成的封固体MR的密合性低,所以封固体MR容易从银膜AGF剥离。即,作为探讨例中的改善的余地,在探讨例中,因直接接触的银膜AGF和封固体MR的密合性低,所以封固体MR容易从银膜AGF剥离。
接着,作为探讨例中存在的进一步的改善的余地,在探讨例中,如图7所示,来自封固体MR的应力可能集中在半导体芯片CHP1的端部。即,在探讨例中,因向半导体芯片CHP1的端部的应力集中,为导致在半导体芯片CHP1的背面和经加压的烧结构造的Ag层AGL(SIN)之间的界面容易产生裂纹。
与之相对,如图6所示,在本实施方式中,在从芯片搭载部TAB的上表面上直至半导体芯片CHP的端部侧面形成有由无加压的烧结构造构成的Ag层AGL。其结果是,在由无加压的烧结构造构成的Ag层AGL的表面形成有凹凸,内部成为多孔质的状态,因此,通过封固体MR的一部分进入这些凹凸或孔而带来的锚定效果,与和由无加压的烧结构造构成的Ag层AGL直接接触的封固体MR的接合性变高。进而,因存在由无加压的烧结构造构成的Ag层AGL,避免形成于芯片搭载部TAB的上表面上的银膜AGF和封固体MR之间密合性低的接触。由此,根据本实施方式,通过因设置由无加压的烧结构造构成的Ag层AGL而避免银膜AGF和封固体MR的密合性低的接触这一点、和得到由无加压的烧结构造构成的Ag层AGL的表面的凹凸或内部的孔带来的锚定效果这一点的相辅效果,能够有效抑制封固体MR的剥离。即,根据本实施方式,能够消除探讨例中的改善的余地。
另外,如图6所示,在本实施方式中,来自封固体MR的应力的一部分被由无加压的烧结构造构成的Ag层AGL吸收。其结果,来自封固体MR的应力集中于半导体芯片CHP1的端部的情况被抑制。即,在本实施方式中,由无加压的烧结构造构成的Ag层AGL作为缓和来自封固体MR的应力的缓冲材料起作用。因此,根据本实施方式,向半导体芯片CHP1的端部的应力集中被抑制,其结果是,在半导体芯片CHP1的背面和经加压的烧结构造的Ag层AGL(SIN)之间的截面产生裂纹的情况被抑制。因此,根据本实施方式,也能够消除探讨例中的进一步的改善的余地。
进而,在本实施方式中,也能够获得以下所示的优点。即,如本实施方式中的烧结构造的Ag层由经加压的烧结构造的Ag层AGL(SIN)和无加压的烧结构造的Ag层AGL形成可知,本实施方式中的烧结构造的Ag层形成为比半导体芯片CHP1的平面尺寸大。这意味着,即使在半导体芯片CHP1的搭载位置稍微产生错位,半导体芯片CHP1也不会从烧结构造的Ag层溢出而被配置在烧结构造的Ag层上。即,根据本实施方式,由于烧结构造的Ag层形成为比半导体芯片CHP1的平面尺寸大,所以即使在半导体芯片CHP1的搭载位置产生错位,也能够增大能够将半导体芯片CHP1配置于烧结构造的Ag层上的余量。其结果,根据本实施方式,即使在半导体芯片CHP1的搭载位置产生了错位的情况下,也能够可靠地进行半导体芯片CHP1和烧结构造的Ag层的电连接。
如上,根据本实施方式的半导体器件,不仅能够消除探讨例中存在的改善的余地,而且对于半导体芯片CHP1的错位也能够实现可靠的电连接,在这一点上也能够提高半导体器件的可靠性。
另外,在本实施方式中,在被芯片搭载部TAB和半导体芯片CHP1夹持的区域形成由经加压的烧结构造构成的Ag层AGL(SIN),并且,在从芯片搭载部TAB的上表面上直至半导体芯片CHP1的端部侧面也形成由无加压的烧结构造构成的Ag层AGL。这意味着,根据本实施方式的半导体器件,不仅能够利用由经加压的烧结构造构成的Ag层AGL(SIN),还能够利用由无加压的烧结构造构成的Ag层AGL进行芯片搭载部TAB和半导体芯片CHP1的电连接。因此,根据本实施方式,由于能够使有助于芯片搭载部TAB和半导体芯片CHP1的电连接的烧结构造的Ag层的体积增加,所以能够降低芯片搭载部TAB和半导体芯片CHP1的连接电阻。因此,根据本实施方式的半导体器件,能够实现半导体器件的性能提高。
如上,根据本实施方式的特征点,不仅能够消除探讨例中存在的改善的余地,而且还具有上述的优点,由此,在能够实现半导体器件的可靠性和性能两者的提高这一点,能够获得探讨例的半导体器件中无法获得的显著的效果。
<实施方式的半导体器件的制造方法>
本实施方式的半导体器件如上构成,以下,参照附图说明该制造方法。
首先,参照流程图简单说明本实施方式的半导体器件的制造工序,之后,参照与各工序对应的附图详细进行说明。
图8是表示本实施方式的半导体器件的制造工序的流程的流程图。图8中,准备形成有集成电路的晶片,通过对该晶片实施切片,将形成于晶片的芯片区域单片化,从晶片取得多个半导体芯片(S101)。
接着,准备成为芯片搭载部的头部,将该头部置于夹具上(S102)。之后,例如使用丝网印刷法,在头部上涂敷溶剂中含有银颗粒的膏(S103)。然后,使涂敷于头部上的膏干燥,形成多孔质状的Ag层(S104)。
接着,在Ag层上搭载了半导体芯片后(S105),对Ag层实施加热处理及加压处理,由此烧结Ag层(S106)。由此,能够形成烧结构造的Ag层。
之后,准备引线框架(L/F),将头部和引线框架置于搬运夹具上(S107)。然后,将溶剂中含有银颗粒的膏向形成于半导体芯片上及引线框架上的引线的一部分供给,以横跨半导体芯片和引线的方式隔着膏搭载夹片。
接着,将置于搬运夹具上的头部和引线框架搬入烘烤炉实施加热处理,由此,使膏烧结,形成烧结构造的Ag层(S109)。由此,使夹片与烧结构造的Ag层电连接。
接着,在从搬运夹具取出了头部和引线框架之后(S110),将形成于半导体芯片的电极焊盘和引线利用铝导线进行导线键合,将其电连接(S111)。之后,将半导体芯片用由树脂构成的封固体封固(S112)。之后,实施引线成形工序或标记工序。如上,能够制造本实施方式的半导体器件。
以下,具体来说,参照附图说明本实施方式的半导体器件的制造工序。
1.芯片搭载部的准备工序
首先,如图9的(a)及图9的(b)所示,准备芯片搭载部TAB。该芯片搭载部TAB例如形成矩形形状,由以铜为主成分的材料构成。
2.芯片搭载工序
接着,如图9的(a)及图9的(b)所示,在芯片搭载部TAB上,例如通过使用丝网印刷法,涂敷溶剂中含有银颗粒的膏PST1。即,将溶剂中含有多个Ag的薄片的膏PST1供给到芯片搭载部TAB上。此时,膏PST1以大致矩形形状在芯片搭载部TAB上的区域涂敷有多个,并在所涂敷的大致矩形形状的角部的一部分形成切缺部NT。
接着,如图10的(a)及图10的(b)所示,将涂敷有膏PST1的芯片搭载部TAB配置于加热板HP上,对膏PST1实施加热处理。由此,使膏PST1干燥,形成多孔质状的Ag层AGL。即,通过加热膏PST1,使膏PST1中的溶剂挥发,在芯片搭载部TAB上形成Ag层AGL。该干燥工序是为了抑制在Ag层上搭载了半导体芯片后残存于Ag层的溶剂挥发而导致在半导体芯片和Ag层之间产生空隙的切缺而实施的。在该干燥工序中,虽使成为空隙的发生原因的溶剂挥发,但同时因形成多孔质状的Ag层AGL而使得粘性(粘接性)也消失。
之后,如图11的(a)及图11的(b)所示,以与芯片搭载部TAB接触的方式供给临时固定材料TA。具体来说,如图11的(a)所示,在切缺部NT周边附近的芯片搭载部TAB上形成临时固定材料TA。该临时固定材料TA由具有粘性的材料构成,例如,作为临时固定材料TA,能够使用具有180℃左右的熔点的低熔点焊锡膏、具有粘性的挥发性溶剂、溶剂中含有银颗粒的膏等。特别是,作为溶剂中含有银颗粒的膏,还能够使用与涂敷于芯片搭载部TAB上的膏PST1同样的材料,为了增加粘性,还能够使用相较于膏PST1增加了溶剂成分的膏。
接着,如图12的(a)及图12的(b)所示,将半导体芯片CHP1及半导体芯片CHP2搭载于芯片搭载部TAB上的Ag层AGL上。此时,形成于半导体芯片CHP1的下层的Ag层AGL的平面尺寸比半导体芯片CHP1的平面尺寸大,俯视时,Ag层AGL的一部分从半导体芯片CHP1溢出。同样地,形成于半导体芯片CHP2的下层的Ag层AGL的平面尺寸比半导体芯片CHP2的平面尺寸大,俯视时,Ag层AGL的一部分从半导体芯片CHP2溢出。进而,在本实施方式中,以半导体芯片CHP1的背面的一部分不与临时固定材料TA接触的方式将半导体芯片CHKP1搭载于Ag层AGL上。同样地,以半导体芯片CHP2的背面的一部分与临时固定材料TA接触的方式将半导体芯片CHKP2搭载于Ag层AGL上。
由此,半导体芯片CHP1及半导体芯片CHP2通过具有粘性的临时固定材料TA固定。在此,从可靠地固定半导体芯片CHP1的观点出发,如图12的(a)所示,优选在设置于所涂敷的大致矩形形状的对角线上的角部设置一对切缺部NT,在该一对切缺部NT形成临时固定材料TA。同样,从可靠地观点半导体芯片CHP2的观点出发,如图12的(a)所示,优选在配置于所涂敷的大致矩形形状的对角线上的角部设置一对切缺部NT,在该一对切缺部NT形成临时固定材料TA。
在本实施方式中,如图12的(a)所示,在芯片搭载部TAB上搭载形成有IGBT的半导体芯片CHP1、和形成有二极管的半导体芯片CHP2。
在此,在形成有二极管的半导体芯片CHP2上,形成于半导体芯片CHP2的背面的阴极电极焊盘以与Ag层AGL及临时固定材料TA接触的方式配置。其结果,形成于半导体芯片CHP2的表面的阳极电极焊盘朝上。
另一方面,在形成有IGBT的半导体芯片CHP1中,形成于半导体芯片CHP1的背面的集电极以与Ag层AGL及临时固定材料TA接触的方式配置。由此,半导体芯片CHP2的阴极电极焊盘和半导体芯片CHP1的集电极经由芯片搭载部TAB电连接。另外,形成于半导体芯片CHP1的表面的发射极焊盘、及多个电极焊盘(多个信号电极焊盘)朝上。
此外,形成有IGBT的半导体芯片CHP1和形成有二极管的半导体芯片CHP2的搭载顺序可以是半导体芯片CHP1在前,半导体芯片CHP2在后,也可以是半导体芯片CHP2在前,半导体芯片CHP1在后。
接着,如图13的(a)及图13的(b)所示,在将经由临时固定材料TA及Ag层AGL连接的芯片搭载部TAB和半导体芯片CHP1(CHP2)隔着缓冲材料CS用压头PH夹持的状态下,实施加热处理(250℃左右)和加压处理。由此,被半导体芯片CHP1和芯片搭载部TAB夹持的Ag层AGL被烧结,形成经加压的烧结构造的AG层AGL(SIN)。同样地,被半导体芯片CHP2和芯片搭载部TAB夹持的Ag层AGL被烧结,形成经加压的烧结构造的AG层AGL(SIN)。另一方面,从半导体芯片CHP1溢出的Ag层AGL未被实施加压处理而仅实施加热处理,因此,形成无加压的烧结构造的Ag层AGL。同样地,从半导体芯片CHP2溢出的Ag层AGL未被实施加压处理而仅实施加热处理,因此,形成无加压的烧结构造的Ag层AGL。如上,通过对半导体芯片CHP1及半导体芯片CHP2施加热量和压力,能够将半导体芯片CHP1的集电极和烧结构造的Ag层(经加压的烧结构造的Ag层AGL(SIN)+无加压的烧结构造的Ag层AGL)电连接。同样地,能够将半导体芯片CHP2的阴极电极和烧结构造的Ag层(经加压的烧结构造的Ag层AGL(SIN)+无加压的烧结构造的Ag层AGL)电连接。
在此,通过实施采用压头PH的加热处理及加压处理,临时固定材料TA根据构成的材料的种类,成为以下的状态。具体来说,例如,在临时固定材料TA由低熔点焊锡膏构成的情况下,低熔点焊锡膏熔融,在实施了加热处理及加压处理后,低熔点焊锡会残存。该情况下,芯片搭载部TAB和半导体芯片CHP1通过经加压的烧结构造的Ag层AGL(SIN)、无加压的烧结构造的Ag层AGL、低熔点焊锡而电连接。另一方面,例如,在临时固定材料TA由挥发性溶剂构成的情况下,基本上挥发性溶剂挥发,临时固定材料TA消失,但有时挥发性溶剂中所含的有机成分(碳成分)作为痕迹而残留。另外,例如,在临时固定材料TA由溶剂中含有银颗粒的膏构成的情况下,形成烧结构造的Ag层。
特别是,在作为临时固定材料TA使用挥发性溶剂的情况下,形成于切缺部NT的周围附近的挥发性溶剂消失,因此,半导体芯片CHP1的背面及半导体芯片CHP2的背面具有不与烧结构造的Ag层(经加压的烧结构造的Ag层AGL(SIN)+无加压的烧结构造的Ag层AGL)电连接的部分。即,在作为临时固定材料TA使用挥发性溶剂的情况下,在切缺部NT的周围附近存在空间。即,在没有与半导体芯片CHP1的背面的烧结构造的Ag层电连接的部分和芯片搭载部TAB的上表面之间存在空间,在该空间埋入有构成在后述的工序中形成的封固体的树脂。同样地,在半导体芯片CHP2的背面的没有与烧结构造的Ag层电连接的部分和芯片搭载部TAB的上表面之间存在空间,在该空间埋入由构成在后述工序中形成的封固体的树脂。
3.引线框架配置工序
接着,如图14的(a)及图14的(b)所示,准备引线框架LF。在引线框架LF上形成有多个引线LD1和多个引线LD2。
之后,如图14的(b)所示,在搭载有半导体芯片CHP1及半导体芯片CHP2的芯片搭载部TAB的上方,使用夹具JG配置引线框架LF。此时,形成IGBT的半导体芯片CHP1被配置在接近引线LD2的位置,形成二极管的半导体芯片CHP2被配置在接近引线LD1的位置。即,以俯视时夹在引线LD1和半导体芯片CHP1之间的方式搭载半导体芯片CHP2,且以夹在引线LD2和半导体芯片CHP2之间的方式配置半导体芯片CHP1。而且,形成有IGBT的半导体芯片CHP1的发射极焊盘被配置于引线LD1侧,且多个电极焊盘(信号电极焊盘)被配置于引线LD2侧。通过这样的配置关系,在搭载有半导体芯片CHP1及半导体芯片CHP2的芯片搭载部TAB的上方配置引线框架LF。
4.电连接工序
接着,在半导体芯片CHP2的阳极电极焊盘上例如形成溶剂中含有银颗粒的膏。之后,在半导体芯片CHP1的发射极焊盘上例如也形成溶剂中含有银颗粒的膏。进而,在引线LD1的一部区域上例如形成溶剂中含有银颗粒的膏。即,在引线LD1上具有能够连接后述的夹片的引线柱部,在该引线柱部形成溶剂中含有银颗粒的膏。该膏可以是与图9所示的膏PST1相同的材料成分,也可以是不同的材料成分。
之后,如图15的(a)及图15的(b)所示,准备夹片CLP,跨过引线LD1上、半导体芯片CHP2上和半导体芯片CHP1上地搭载夹片CLP。具体来说,以横跨引线LD1上、半导体芯片CHP2上和半导体芯片CHP1的方式,经由溶剂中不含银颗粒的膏配置夹片CLP。即,以俯视时不与半导体芯片CHP1的发射极焊盘、半导体芯片CHP2的阳极电极焊盘和引线LD1的一部分(引线柱部)重合的方式,经由膏配置夹片CLP。
这样,在以横跨引线LD1上、半导体芯片CHP2上和半导体芯片CHP1的方式经由膏配置夹片CLP之后,实施加热处理(烘烤处理)。由此,溶剂成分自膏挥发,形成无加压的烧结构造的Ag层AGL。即,在该工序中,未实施加压处理,因此,膏成为无加压的烧结构造的Ag层AGL。如上,引线LD1、形成于半导体芯片CHP2的阳极电极焊盘、形成于半导体芯片CHP1的发射极焊盘经由无加压的烧结构造的Ag层AGL与夹片CLP电连接。
接着,实施将半导体芯片CHP1和引线LD2利用导线W连接的导线键合工序。具体来说,如图16的(a)及图16的(b)所示,将形成于半导体芯片CHP1的表面的信号电极焊盘和形成于引线框架LF的引线LD2(信号引线)通过由铝构成的导线W连接。由此,实施导线键合工序。此时,在本实施方式中,引线LD2配置于与连接有夹片CLP的引线LD1相反侧,因此,能够不考虑夹片CLP带来的干涉而实施导线键合工序。之后,将夹具JG拆下,结束导线键合工序。
5.封固(模塑)工序
接着,如图17的(a)及图17的(b)所示,将半导体芯片CHP1、半导体芯片CHP2、芯片搭载部TAB的一部分、引线LD1的一部分、多个引线LD2各自的一部分、夹片CLP及导线W封固,例如形成由树脂构成的封固体MR。在此,如图6所示,在本实施方式中,以覆盖从芯片搭载部TAB的上表面上至半导体芯片CHP1的端部侧面而形成的无加压的烧结构造的Ag层AGL的方式形成了封固体MR。此时,无加压的烧结构造的Ag层AGL的密度比经加压的烧结构造的Ag层AGL(SIN)的密度低,因此,构成封固体MR的树脂的一部分浸透无加压的烧结构造的Ag层AGL内的多个Ag间(多个Ag薄片之间)。
此外,封固体MR具有上表面、与上表面相反侧的下表面、在其厚度方向上位于上表面和下表面之间的第一侧面及与第一侧面相对的第二侧面。图17(a)中,图示第一侧面的边S1和第二侧面的边S2。进而,在封固体MR上,引线LD1从封固体MR的第一侧面(边S1)突出,且多个引线LD2从封固体MR的第二侧面(边S2)突出。
6.封装镀敷工序
之后,图中未图示,将设置于引线框架LF上的连接杆切断。然后,在从封固体MR的下表面露出的芯片搭载部TAB、引线LD1的一部分的表面、引线LD2的一部分的表面形成作为导体膜的镀敷层。即,在引线LD1的从封固体MR露出的部分、多个引线LD2的从封固体MR露出的部分及芯片搭载部TAB的下表面形成镀敷层。
7.标记工序
接着,在由树脂构成的封固体MR的表面形成产品名或型号等信息(标记)。此外,作为标记的形成方法,能够使用利用印刷方式进行印字的方法或通过对封固体的表面照射激光而进行刻印的方法。
8.单片化工序
接着,通过将引线LD1的一部分及多个引线LD2各自的一部分切断,从引线框架LF分离引线LD1及多个引线LD2。由此,能够制造本实施方式的半导体器件。之后,成形引线LD1及多个引线LD2的各引线。然后,例如在实施了测试电特性的测试工序后,出厂被判定为成品的半导体器件。如上,能够制造本实施方式的半导体器件。
<实施方式的半导体器件的制法上的特征>
接着说明本实施方式的制法上的基本思想。本实施方式的制法上的基本思想是尽量不在成为多孔质状态的Ag层的表面上形成临时固定材料,同时使用具有粘(tack)性的临时固定材料将搭载于Ag层上的半导体芯片固定。即,在本实施方式中,考虑到当单纯在成为多孔质状态的Ag层上搭载半导体芯片时,由于在多孔质状态的Ag层不存在粘性,所以容易产生半导体芯片的错位,考虑通过具有粘性的临时固定材料固定半导体芯片。但是,在本实施方式中,考虑到当向成为多孔质状态的Ag层的表面上供给临时固定材料时,临时固定材料浸入(渗透)到多孔质状态的Ag层,由此,用于保持半导体芯片的位置的临时固定材料的量不稳定,因此无法有效抑制半导体芯片的错位的情况。进而,在本实施方式中,考虑到通过在半导体芯片搭载工序之后实施的加热工序及加压工序,浸入到Ag层的临时固定材料的溶剂成分挥发,但挥发的溶剂成分没有泄漏路径,而被半导体芯片的下层俘获,从而成为空隙的产生要因。因此,在本实施方式中,考虑上述的点,进行了将下述基本思想具体化的研究,即,尽量不在成为多孔质状态的Ag层的表面上形成临时固定材料,同时,使用具有粘性的临时固定材料固定搭载于Ag层上的半导体芯片。
在本实施方式中,为了实现上述的基本思想,具有如下的特征:以具有与芯片搭载部接触的部分的方式供给临时固定材料,且以半导体芯片的背面的一部分与临时固定材料接触的方式将半导体芯片搭载于Ag层上。由此,根据本实施方式,由于避免在Ag层的表面上形成临时固定材料整体,所以与在Ag层的表面上形成临时固定材料整体的情况相比,能够抑制临时固定材料向Ag层的浸入。其结果,根据本实施方式,能够抑制临时固定材料向Ag层的浸入引起的半导体芯片的错位或空隙的产生,由此,能够提高本实施方式的半导体器件的可靠性。
以下,说明将本实施方式的特征点具体化了的结构例。图18是表示通过形成于芯片搭载部TAB上的临时固定材料TA来固定半导体芯片CHP1的状态的示意图。特别是,图18的(a)是示意性表示利用形成于芯片搭载部TAB上的临时固定材料TA来固定半导体芯片CHP1的状态的放大俯视图,图18的(b)是图18的(a)的A-A线的剖视图。
图18的(a)中,在芯片搭载部TAB上形成有通过干燥工序进行了干燥的多孔质状态的Ag层AGL,在该Ag层AGL上搭载有半导体芯片CHP1。然后,在俯视时在与由半导体芯片CHP1的相互交叉的边SD1和边SD2的交点附近区域构成的角部CNR重合的位置形成有临时固定材料TA,以半导体芯片CHP1的角部CNR和临时固定材料TA接触的方式将半导体芯片CHP1搭载于Ag层AGL上。具体来说,如图18的(a)所示,在与半导体芯片CHP1的角部CNR对应的平面位置,在形成于半导体芯片CHP1的下层的Ag层AGL形成切缺部NT1。然后,在该切缺部NT1形成有临时固定材料TA。
即,在本实施方式中,在Ag层AGL形成有切缺部NT1,在从该切缺部NT1露出的芯片搭载部TAB的上表面上形成有临时固定材料TA。然后,以与从切缺部NT1露出的芯片搭载部TAB的上表面上接触的方式形成的临时固定材料TA、和搭载于Ag层AGL上的半导体芯片接触。因此,在从半导体芯片CHP1的表面俯视时,半导体芯片CHP1的角部CNR不与Ag层AGL重合,在包含该不重合的区域在内的芯片搭载部TAB上形成有临时固定材料TA。
由此,根据图18的(a)及图18的(b)所示的结构例,可知实现了以具有与芯片搭载部TAB接触的部分的方式供给临时固定材料TA,且以半导体芯片CHP1的背面的一部分与临时固定材料TA接触的方式将半导体芯片CHP1搭载于Ag层AGL上的本实施方式的特征点。特别是,在图18的(a)及图18的(b)所示的结构例中,临时固定材料TA与Ag层AGL的侧面接触,但由于与Ag层AGL的表面上完全不接触,所以能够有效抑制临时固定材料TA向Ag层AGL的浸入。其结果,根据图18的(a)及图18的(b)所示的结构例,能够增大抑制因临时固定材料TA向Ag层AGL的浸入引起的半导体芯片产生错位或空隙的效果。
在此,认为在临时固定材料TA与Ag层AGL的侧面接触的情况下,临时固定材料TA的溶剂成分会从Ag层AGL的侧面浸入。因此,从更有效地防止临时固定材料TA向Ag层AGL的浸入的观点出发,在图18的(a)及图18的(b)所示的结构例中,能够考虑期望以临时固定材料TA也不与Ag层AGL的侧面接触的方式构成。
但是,本实施方式的基本思想不限于此,也可以使临时固定材料TA与Ag层AGL的侧面接触。这是因为,在该结构的情况下,虽然考虑到多少产生向AG层AGL的浸入,但与将临时固定材料整体形成于Ag层的表面上的结构相比,能够降低临时固定材料向Ag层的浸入量。
在此,在临时固定材料TA与Ag层AGL的侧面接触的情况下,尽量降低临时固定材料TA中包含的溶剂成分从Ag层AGL的侧面浸入的量,使用于保持半导体芯片CHP1的位置的临时固定材料TA的量稳定至为重要。因此,在临时固定材料TA与Ag层AGL的侧面接触的情况下,最好在供给临时固定材料TA的工序之后,立即尽量减小临时固定材料TA和Ag层AGL的侧面的接触面积。例如,最好在供给临时固定材料TA的工序之后,立即使临时固定材料TA的与芯片搭载部TAB接触的部分的面积比临时固定材料TA的与Ag层AGL的侧面接触的部分的面积大。另外,不仅供给临时固定材料TA的工序之后,在之后的半导体芯片搭载工序中,也期望临时固定材料TA的量稳定,因此,最好使临时固定材料TA的与芯片搭载部TAB接触的部分的面积比临时固定材料TA的与Ag层AGL的侧面接触的部分的面积大。
此外,在本实施方式中,如图18的(b)所示,半导体芯片CHP1的角部CNR不与Ag层AGL重合,在包含该不重合的区域在内的芯片搭载部TAB上形成有临时固定材料TA。即,如图18的(a)所示,在Ag层AGL形成了切缺部NT1的结果是,与切缺部NT1相对应地,在半导体芯片CHP1的角部CNR与芯片搭载部TAB之间形成有间隙,在该间隙填充有临时固定材料TA(参照图18的(b))。因此,如图18的(b)所示,在芯片搭载工序中,半导体芯片CHP1通过临时固定材料TA固定。之后,为了将Ag层AGL制成烧结构造的Ag层,实施加热工序及加压工序。此时,例如,在临时固定材料TA由挥发性溶剂形成的情况下,在实施加热工序及加压工序时,临时固定材料TA挥发。其结果为,在半导体芯片CHP1的角部CNR和芯片搭载部TAB之间的填充有临时固定材料TA的部位产生间隙。例如如图19所示,在该间隙中,通过在之后的工序中实施的树脂封固工序(模塑工序),填充构成封固体MR的树脂的一部分。即,在临时固定材料TA由挥发性溶剂形成的情况下,如图19所示,在实施了模塑工序之后,在半导体芯片CHP1的角部CNR和芯片搭载部TAB的上表面之间产生的间隙埋入封固体MR的一部分。
<变形例1>
实施方式的特征点是,以具有与芯片搭载部接触的部分的方式供给临时固定材料,且以半导体芯片的背面的一部分与临时固定材料接触的方式将半导体芯片搭载于Ag层上。以下,对实现该特征点的结构的一例即变形例1进行说明。
图20是表示在本变形例1中利用形成于芯片搭载部TAB上的临时固定材料TA固定了半导体芯片CHP1的状态的示意图。特别是,图20的(a)是示意性表示利用形成于芯片搭载部TAB上的临时固定材料TA固定了半导体芯片CHP1的状态的放大俯视图,图20的(b)是图20的(a)的A-A线的剖视图。
本变形例1中,如图20的(a)所示,在与半导体芯片CHP1的角部CNR对应的平面位置,在形成于半导体芯片CHP1的下层的Ag层AGL上形成有切缺部NT1。然后,如图20的(b)所示,在从该切缺部NT2露出的芯片搭载部TAB的上表面上形成有临时固定材料TA,进而,临时固定材料TA的一部分也形成于Ag层AGL的表面上。
在像这样构成的本变形例1中,与图18的(a)及图18的(b)所示的实施方式不同,在Ag层AGL的表面上也形成有临时固定材料TA的一部分。但是,在该情况下,由于不将临时固定材料TA整体形成于Ag层AGL的表面上,所以与将临时固定材料TA整体形成于Ag层AGL的表面上的情况相比,能够抑制临时固定材料TA向Ag层AGL浸入。其结果为,根据本变形例1,能够抑制临时固定材料TA向Ag层AGL的浸入引起的半导体芯片CHP1的错位或空隙的产生,由此,能够提高本实施方式的半导体器件的可靠性。
特别是,在本变形例1中,临时固定材料TA的一部分形成于Ag层AGL的表面上,但形成有临时固定材料TA的一部分的区域是Ag层AGL的端部附近区域。因此,例如,即使存在临时固定材料TA中所含的溶剂成分向Ag层AGL的浸入,浸入了的溶剂成分也能够容易地从Ag层AGL的端部侧面挥发,其结果为,空隙的产生被抑制。
但是,如本变形例1那样,在临时固定材料TA的一部分与Ag层AGL的表面接触的情况下,尽量降低临时固定材料TA中所含的溶剂成分从Ag层AGL的表面的浸入量,使用于保持半导体芯片CHP1的位置的临时固定材料TA的量稳定至为重要。因此,在临时固定材料TA的一部分与Ag层AGL的表面接触的情况下,最好在供给临时固定材料TA的工序之后,立即尽量减小临时固定材料TA的一部和Ag层AGL的表面的接触面积。例如,最好在供给临时固定材料TA的工序之后,立即使临时固定材料TA的与芯片搭载部TAB接触的部分的面积(S1)比临时固定材料TA的与Ag层AGL的侧面接触的部分的面积(S2)大。此外,不仅供给临时固定材料TA的工序之后,在之后的半导体芯片搭载工序中,也期望临时固定材料TA的量稳定,因此,最好使临时固定材料TA的与芯片搭载部TAB接触的部分的面积(S1)比临时固定材料TA的与Ag层AGL的侧面接触的部分的面积(S2)大。
<变形例2>
实施方式的特征点是,以具有与芯片搭载部接触的部分的方式供给临时固定材料,且以半导体芯片的背面的一部分与临时固定材料接触的方式将半导体芯片搭载于Ag层上。以下,对实现该特征点的结构的一例即变形例2进行说明。
图21是表示在本变形例2中利用形成于芯片搭载部TAB上的临时固定材料TA固定了半导体芯片CHP1的状态的示意图。特别是,图21的(a)是示意性表示利用形成于芯片搭载部TAB上的临时固定材料TA固定了半导体芯片CHP1的状态的放大俯视图,图21的(b)是图21的(a)的A-A线的剖视图。
本变形例2中,如图21的(a)所示,在与半导体芯片CHP1的角部CNR对应的平面位置,在形成于半导体芯片CHP1的下层的Ag层AGL未形成切缺部。然后,如图21的(b)所示,Ag层AGL具有从半导体芯片CHP1的角部CNR溢出的部分。其结果,在本变形例2中,在芯片搭载部TAB的上表面上形成有临时固定材料TA,进而,临时固定材料TA的一部分也形成于Ag层AGL的表面上。
在这样构成的本变形例2中,与图18的(a)及图18的(b)所示的实施方式不同,在Ag层AGL的表面上也形成有临时固定材料TA的一部分。特别是,在本变形例2中,临时固定材料TA的与芯片搭载部TAB接触的部分的面积(S1)比临时固定材料TA的与Ag层AGL的表面接触的部分的面积(S2)小。但是,在该情况下,由于也不在Ag层AGL的表面上形成临时固定材料TA整体,所以与将临时固定材料TA整体形成于Ag层AGL的表面上的情况相比,能够抑制临时固定材料TA向Ag层AGL浸入。其结果为,根据本变形例2,能够抑制临时固定材料TA向Ag层AGL的浸入引起的半导体芯片CHP1的错位或空隙的产生。由此,能够提高本实施方式的半导体器件的可靠性。
特别是,在本变形例2中,也与变形例1相同,将临时固定材料TA的一部分形成于Ag层AGL的表面上,但形成有临时固定材料TA的一部分的区域是Ag层AGL的端部附近区域。因此,例如,即使存在临时固定材料TA中所含的溶剂成分向Ag层AGL的浸入,所浸入的溶剂成分也能够容易地从Ag层AGL的端部侧面挥发,其结果为,使空隙的产生被抑制。
此外,本变形例2中,在Ag层AGL未设置切缺部,Ag层AGL具有从半导体芯片CHP1的角部CNR溢出的部分。即,根据本变形例2,在俯视时,不仅下层的Ag层AGL从半导体芯片CHP1的边S1及边S2溢出,而且在半导体芯片CHP1的角部CNR,下层的Ag层AGL也溢出。这意味着,根据本变形例2的结构,在半导体芯片CHP1的角部CNR,也实现图6所示的构造。而且,根据图6所示的构造,由于能够抑制向半导体芯片CHP1的应力集中,所以根据对容易产生应力集中的半导体芯片CHP1的角部CNR应用图6所示的构造的本变形例2,获得能够抑制半导体芯片CHP1的角部的应力集中的效果。
以上,对于本发明人提出的发明,基于其实施方式进行了具体说明,但本发明不限于上述实施方式,在不脱离其宗旨的范围内能够进行各种变更。
附图标记说明
AGL Ag层
CHP1 半导体芯片
CHP2 半导体芯片
LD1 引线
LD2 引线
LF 引线框架
PST1 膏
TA 临时固定材料
TAB 芯片搭载部
Claims (19)
1.一种半导体器件的制造方法,其具有:
(a)准备具有芯片搭载部和多个引线的引线框架的工序;
(b)将在第一溶剂中含有多个第一Ag的薄片的第一膏向所述芯片搭载部上供给的工序;
(c)通过加热所述第一膏,使所述膏中的所述第一溶剂挥发,在所述芯片搭载部上形成第一Ag层的工序;
(d)将具有形成有第一电极焊盘的表面、和与所述表面为相反侧的面且形成有第二电极的背面的半导体芯片搭载于所述芯片搭载部上的所述第一Ag层上的工序;以及
(e)在所述(d)工序之后,对所述半导体芯片施加热和压力,将所述半导体芯片的所述第二电极和所述第一Ag层电连接的工序,
所述(d)工序包含:
(d1)以与所述芯片搭载部接触的方式供给第一材料的工序;
(d2)以使所述半导体芯片的所述背面的一部分与所述第一材料接触的方式将所述半导体芯片搭载于所述第一Ag层上的工序。
2.根据权利要求1所述的半导体器件的制造方法,其中,
所述半导体芯片的所述背面具有第一边、与所述第一边交叉的第二边、以及由所述第一边和所述第二边构成的第一角部,
在所述(d2)工序中,以使所述半导体芯片的所述第一角部与所述第一材料接触的方式将所述半导体芯片搭载于所述第一Ag层上。
3.根据权利要求1所述的半导体器件的制造方法,其中,
在所述(d1)工序之后,所述第一材料的与所述芯片搭载部接触的部分的面积比所述第一材料的与所述第一Ag层接触的部分的面积大。
4.根据权利要求1所述的半导体器件的制造方法,其中,
在所述(e)工序之后,所述第一材料没有残留在所述芯片搭载部上。
5.根据权利要求4所述的半导体器件的制造方法,其中,
所述第一材料是挥发性的材料。
6.根据权利要求1所述的半导体器件的制造方法,其中,还具有:
(f)在所述(e)工序之后,将在第二溶剂中含有多个第二Ag的薄片的第二膏向所述半导体芯片的所述第一电极焊盘、及所述多个引线中的第一引线的一部分供给的工序;
(g)在所述(f)工序之后,以与所述第一电极焊盘上的所述第二膏和所述第一引线上的所述第二膏接触的方式将导体板搭载于所述半导体芯片和所述第一引线上的工序;以及
(h)在所述(g)工序之后,加热所述第二膏,使所述第二膏中的所述第二溶剂挥发,由此形成第二Ag层,使所述导体板经由所述第二Ag层与所述半导体芯片的所述第一电极焊盘和所述第一引线电连接的工序。
7.根据权利要求1所述的半导体器件的制造方法,其中,
所述半导体芯片包含绝缘栅双极型晶体管,
所述第一电极焊盘是所述绝缘栅双极型晶体管的发射极,
所述第二电极是所述绝缘栅双极型晶体管的集电极。
8.一种半导体器件,其具有:
半导体芯片,其具有形成有第一电极焊盘的表面、和与所述表面为相反侧的面且形成有第二电极的背面;
芯片搭载部,其具有搭载有所述半导体芯片的第一主面、和作为与所述第一主面相反一侧的面的第二主面;
第一引线,其经由导体板与所述半导体芯片的所述第一电极焊盘电连接;以及
封固体,其将所述半导体芯片和所述导体板树脂封固,
所述半导体芯片的所述第二电极经由由多个第一Ag的薄片形成的第一Ag层与所述芯片搭载部的所述第一主面电连接,
在从所述半导体芯片的所述表面俯视观察时,所述第一Ag层的与所述半导体芯片重合的第一部分为处于经加压的状态的烧结构造,
在从所述半导体芯片的所述表面俯视观察时,所述第一Ag层的不与所述半导体芯片重合的第二部分由处于经加压的状态的烧结构造的压出部分、以及覆盖所述压出部分的处于无加压状态的烧结构造构成,
处于经加压的状态的烧结构造中的第一Ag的密度比处于无加压状态的烧结构造中的第一Ag的密度高。
9.根据权利要求8所述的半导体器件,其中,
所述半导体芯片的所述背面具有不与所述第一Ag层直接接触的部分。
10.根据权利要求9所述的半导体器件,其中,
在所述半导体芯片的所述背面的不与所述第一Ag层直接接触的部分与所述芯片搭载部的所述第一主面之间配置有所述封固体的一部分。
11.根据权利要求8所述的半导体器件,其中,
所述半导体芯片的所述背面具有由第一边、与所述第一边交叉的第二边、以及由所述第一边和所述第二边构成的第一角部,
在从所述半导体芯片的所述表面俯视观察时,所述半导体芯片的所述第一角部不与所述第一Ag层重合。
12.根据权利要求11所述的半导体器件,其中,
在所述半导体芯片的所述第一角部与所述芯片搭载部的所述第一主面之间配置有所述封固体的一部分。
13.根据权利要求8所述的半导体器件,其中,
所述封固体的一部分浸透到所述第一Ag层的所述第二部分的所述多个第一Ag间。
14.根据权利要求8所述的半导体器件,其中,
所述第一Ag层的所述第二部分具有其厚度比所述第一Ag层的所述第一部分厚的部分。
15.根据权利要求8所述的半导体器件,其中,
在所述芯片搭载部的所述第一主面上形成有与所述第一Ag层电连接的镀敷层。
16.根据权利要求15所述的半导体器件,其中,
所述镀敷层是Ag镀层,所述Ag镀层的Ag的密度比所述第一Ag层的所述第一部分的所述第一Ag的密度高。
17.根据权利要求8所述的半导体器件,其中,
所述导体板经由由多个第二Ag的薄片形成的第二Ag层与所述半导体芯片的所述第一电极焊盘和所述第一引线电连接。
18.根据权利要求8所述的半导体器件,其中,
在所述半导体芯片的所述背面形成有与所述第一Ag层电连接的Au膜。
19.根据权利要求8所述的半导体器件,其中,
所述半导体芯片包含绝缘栅双极型晶体管,
所述第一电极焊盘与所述绝缘栅双极型晶体管的发射极电连接,
所述第二电极与所述绝缘栅双极型晶体管的集电极电连接。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2015/071043 WO2017013808A1 (ja) | 2015-07-23 | 2015-07-23 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107210233A CN107210233A (zh) | 2017-09-26 |
CN107210233B true CN107210233B (zh) | 2021-07-23 |
Family
ID=57834806
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201580073894.XA Active CN107210233B (zh) | 2015-07-23 | 2015-07-23 | 半导体器件及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10262927B2 (zh) |
JP (1) | JP6450006B2 (zh) |
CN (1) | CN107210233B (zh) |
WO (1) | WO2017013808A1 (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018148168A (ja) * | 2017-03-09 | 2018-09-20 | 日立化成株式会社 | 半導体装置 |
CN112041972A (zh) * | 2018-04-27 | 2020-12-04 | 日东电工株式会社 | 半导体装置制造方法 |
US20210043466A1 (en) | 2019-08-06 | 2021-02-11 | Texas Instruments Incorporated | Universal semiconductor package molds |
WO2021193150A1 (ja) | 2020-03-27 | 2021-09-30 | 三井金属鉱業株式会社 | 仮固定用組成物及び接合構造体の製造方法 |
JP7465414B1 (ja) | 2022-08-31 | 2024-04-10 | 三井金属鉱業株式会社 | 仮固定用組成物、接合構造体の製造方法及び仮固定用組成物の使用 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102693953A (zh) * | 2011-03-22 | 2012-09-26 | 株式会社东芝 | 半导体装置及其制造方法 |
CN104025287A (zh) * | 2011-10-31 | 2014-09-03 | 罗姆股份有限公司 | 半导体装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5282981B2 (ja) * | 2007-12-21 | 2013-09-04 | 株式会社村田製作所 | 素子搭載基板の製造方法 |
TWI456707B (zh) | 2008-01-28 | 2014-10-11 | Renesas Electronics Corp | 半導體裝置及其製造方法 |
JP2010171271A (ja) | 2009-01-23 | 2010-08-05 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2011165871A (ja) * | 2010-02-09 | 2011-08-25 | Denso Corp | 電子装置およびその製造方法 |
DE102010021764B4 (de) * | 2010-05-27 | 2014-09-25 | Semikron Elektronik Gmbh & Co. Kg | Verfahren zur Niedertemperatur Drucksinterverbindung zweier Verbindungspartner |
JP5525335B2 (ja) * | 2010-05-31 | 2014-06-18 | 株式会社日立製作所 | 焼結銀ペースト材料及び半導体チップ接合方法 |
WO2012043545A1 (ja) * | 2010-09-29 | 2012-04-05 | 日立化成工業株式会社 | 接着剤組成物及びそれを用いた半導体装置 |
JP2013041884A (ja) * | 2011-08-11 | 2013-02-28 | Furukawa Electric Co Ltd:The | 半導体装置 |
JP6146007B2 (ja) * | 2012-03-30 | 2017-06-14 | 三菱マテリアル株式会社 | 接合体の製造方法、パワーモジュールの製造方法、パワーモジュール用基板及びパワーモジュール |
US8716864B2 (en) * | 2012-06-07 | 2014-05-06 | Ixys Corporation | Solderless die attach to a direct bonded aluminum substrate |
JP2014127537A (ja) * | 2012-12-26 | 2014-07-07 | Hitachi Power Semiconductor Device Ltd | 導電性接合材料を用いた半導体装置及びその半導体装置の製造方法。 |
JP5975911B2 (ja) | 2013-03-15 | 2016-08-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20180190593A1 (en) * | 2016-12-30 | 2018-07-05 | Intel Corporation | Conductive adhesive layer for semiconductor devices and packages |
-
2015
- 2015-07-23 JP JP2017529432A patent/JP6450006B2/ja active Active
- 2015-07-23 US US15/558,977 patent/US10262927B2/en active Active
- 2015-07-23 CN CN201580073894.XA patent/CN107210233B/zh active Active
- 2015-07-23 WO PCT/JP2015/071043 patent/WO2017013808A1/ja active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102693953A (zh) * | 2011-03-22 | 2012-09-26 | 株式会社东芝 | 半导体装置及其制造方法 |
CN104025287A (zh) * | 2011-10-31 | 2014-09-03 | 罗姆股份有限公司 | 半导体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN107210233A (zh) | 2017-09-26 |
US10262927B2 (en) | 2019-04-16 |
JPWO2017013808A1 (ja) | 2017-10-19 |
JP6450006B2 (ja) | 2019-01-09 |
US20180247884A1 (en) | 2018-08-30 |
WO2017013808A1 (ja) | 2017-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107210233B (zh) | 半导体器件及其制造方法 | |
US8736052B2 (en) | Semiconductor device including diffusion soldered layer on sintered silver layer | |
KR101378792B1 (ko) | 클립리스 및 와이어리스 반도체 다이 패키지 및 그제조방법 | |
US9018744B2 (en) | Semiconductor device having a clip contact | |
US8466548B2 (en) | Semiconductor device including excess solder | |
US11721612B2 (en) | Semiconductor device with connecting member for electrode and method of manufacturing | |
US7754533B2 (en) | Method of manufacturing a semiconductor device | |
US20090230519A1 (en) | Semiconductor Device | |
US20120061819A1 (en) | Semiconductor Module and Method for Production Thereof | |
US9991220B2 (en) | Semiconductor device | |
US7498195B2 (en) | Multi-chip semiconductor connector assembly method | |
CN109616460B (zh) | 电力用半导体装置 | |
CN111276447A (zh) | 双侧冷却功率模块及其制造方法 | |
CN111602233B (zh) | 半导体装置的制造方法 | |
CN113496977A (zh) | 共源共栅半导体装置和制造方法 | |
JP7135293B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US20210384109A1 (en) | Semiconductor device and method of manufacturing the same | |
US11837516B2 (en) | Semiconductor device | |
JP2012191057A (ja) | 電力用半導体装置 | |
CN111354709A (zh) | 半导体装置及其制造方法 | |
CN113056813A (zh) | 半导体装置 | |
JP7254216B2 (ja) | 半導体装置の製造方法 | |
US20230081341A1 (en) | Semiconductor device | |
US20220384283A1 (en) | Semiconductor device and method of manufacturing semiconductor device | |
EP4215508A1 (en) | Substrate and method for producing a substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |