JP5279701B2 - 命令プリフェッチバッファ深さの動的制御を有するデータプロセッサとその方法 - Google Patents

命令プリフェッチバッファ深さの動的制御を有するデータプロセッサとその方法 Download PDF

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JP5279701B2
JP5279701B2 JP2009501622A JP2009501622A JP5279701B2 JP 5279701 B2 JP5279701 B2 JP 5279701B2 JP 2009501622 A JP2009501622 A JP 2009501622A JP 2009501622 A JP2009501622 A JP 2009501622A JP 5279701 B2 JP5279701 B2 JP 5279701B2
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prefetch buffer
instruction
control unit
starvation
cache
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JP2009530753A5 (enExample
JP2009530753A (ja
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ジェフリー ダブリュ スコット
ウィリアム シー モイヤー
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NXP USA Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2009501622A 2006-03-21 2007-02-23 命令プリフェッチバッファ深さの動的制御を有するデータプロセッサとその方法 Active JP5279701B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/385,463 US9304773B2 (en) 2006-03-21 2006-03-21 Data processor having dynamic control of instruction prefetch buffer depth and method therefor
US11/385,463 2006-03-21
PCT/US2007/062651 WO2007109395A2 (en) 2006-03-21 2007-02-23 Data processor having dynamic control of instruction prefetch buffer depth and method therefor

Publications (3)

Publication Number Publication Date
JP2009530753A JP2009530753A (ja) 2009-08-27
JP2009530753A5 JP2009530753A5 (enExample) 2010-04-08
JP5279701B2 true JP5279701B2 (ja) 2013-09-04

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JP2009501622A Active JP5279701B2 (ja) 2006-03-21 2007-02-23 命令プリフェッチバッファ深さの動的制御を有するデータプロセッサとその方法

Country Status (5)

Country Link
US (1) US9304773B2 (enExample)
EP (1) EP1999574B1 (enExample)
JP (1) JP5279701B2 (enExample)
KR (1) KR20080102213A (enExample)
WO (1) WO2007109395A2 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100483305C (zh) * 2006-06-12 2009-04-29 中芯国际集成电路制造(上海)有限公司 用于asic器件功率控制的系统和方法
US7996689B2 (en) * 2006-06-12 2011-08-09 Semiconductor Manufacturing International (Shanghai) Corporation System and method for power control for ASIC device
US9081501B2 (en) * 2010-01-08 2015-07-14 International Business Machines Corporation Multi-petascale highly efficient parallel supercomputer
US10346173B2 (en) * 2011-03-07 2019-07-09 Oracle International Corporation Multi-threaded instruction buffer design
CN103460183B (zh) 2011-03-30 2016-11-23 飞思卡尔半导体公司 控制vles处理器架构内的提前提取的方法和装置
US9104532B2 (en) * 2012-12-14 2015-08-11 International Business Machines Corporation Sequential location accesses in an active memory device
JP5971211B2 (ja) * 2013-08-06 2016-08-17 株式会社デンソー 電子制御装置
US11768689B2 (en) 2013-08-08 2023-09-26 Movidius Limited Apparatus, systems, and methods for low power computational imaging
US10628163B2 (en) 2014-04-17 2020-04-21 Texas Instruments Incorporated Processor with variable pre-fetch threshold
US9256541B2 (en) * 2014-06-04 2016-02-09 Oracle International Corporation Dynamically adjusting the hardware stream prefetcher prefetch ahead distance
US9639396B2 (en) 2014-09-16 2017-05-02 Nxp Usa, Inc. Starvation control in a data processing system
US9541988B2 (en) 2014-09-22 2017-01-10 Western Digital Technologies, Inc. Data storage devices with performance-aware power capping
US10146293B2 (en) * 2014-09-22 2018-12-04 Western Digital Technologies, Inc. Performance-aware power capping control of data storage devices
WO2016092347A1 (en) * 2014-12-13 2016-06-16 Via Alliance Semiconductor Co., Ltd. Distributed hang recovery logic
CN105849705B (zh) * 2014-12-13 2019-06-04 上海兆芯集成电路有限公司 用于检测暂停的逻辑分析器
WO2016092345A1 (en) 2014-12-13 2016-06-16 Via Alliance Semiconductor Co., Ltd. Logic analyzer for detecting hangs
GB2546465B (en) * 2015-06-05 2018-02-28 Advanced Risc Mach Ltd Modal processing of program instructions
US9965206B2 (en) 2015-10-23 2018-05-08 Western Digital Technologies, Inc. Enhanced queue management for power control of data storage device
US20180004512A1 (en) * 2016-06-30 2018-01-04 Intel Corporation System and Method for Out-of-Order Clustered Decoding
US10467141B1 (en) 2018-06-18 2019-11-05 International Business Machines Corporation Process data caching through iterative feedback
US10963249B2 (en) 2018-11-02 2021-03-30 International Business Machines Corporation Processor prefetcher mode governor for switching between prefetch modes
US11163683B2 (en) 2019-08-01 2021-11-02 International Business Machines Corporation Dynamically adjusting prefetch depth
US11301386B2 (en) 2019-08-01 2022-04-12 International Business Machines Corporation Dynamically adjusting prefetch depth
US11327891B2 (en) 2019-09-20 2022-05-10 Samsung Electronics Co., Ltd. Prefetching operations in storage devices

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US632280A (en) * 1899-04-19 1899-09-05 Llewellyn Emerson Pulsifer Ash-sifter.
US4714994A (en) * 1985-04-30 1987-12-22 International Business Machines Corp. Instruction prefetch buffer control
JPS6349938A (ja) * 1986-08-20 1988-03-02 Fujitsu Ltd 命令先取り制御装置
JPS6349937A (ja) 1986-08-20 1988-03-02 Fujitsu Ltd 命令先取り制御装置
JPH0218620A (ja) 1988-07-07 1990-01-22 Toshiba Corp 情報処理装置
JPH02157938A (ja) 1988-12-09 1990-06-18 Matsushita Electric Ind Co Ltd 命令先読み制御装置
JPH02163828A (ja) * 1988-12-16 1990-06-25 Mitsubishi Electric Corp データ処理装置
JP2834289B2 (ja) * 1990-07-20 1998-12-09 株式会社日立製作所 マイクロプロセッサ
JPH0497463A (ja) 1990-08-15 1992-03-30 Nec Corp メッセージバッファに対する実メモリ補給方式
JP2682264B2 (ja) * 1991-05-21 1997-11-26 日本電気株式会社 プログラムカウンタ装置
JPH0728751A (ja) 1993-06-24 1995-01-31 Nec Corp 転送制御装置
IE940855A1 (en) 1993-12-20 1995-06-28 Motorola Inc Data processor with speculative instruction fetching and¹method of operation
JPH07182164A (ja) 1993-12-22 1995-07-21 Nec Ic Microcomput Syst Ltd 中央処理装置
US5623615A (en) 1994-08-04 1997-04-22 International Business Machines Corporation Circuit and method for reducing prefetch cycles on microprocessors
JPH08339289A (ja) * 1995-06-13 1996-12-24 Nec Corp 可変容量バッファメモリ
US5805876A (en) 1996-09-30 1998-09-08 International Business Machines Corporation Method and system for reducing average branch resolution time and effective misprediction penalty in a processor
US6092187A (en) 1997-09-19 2000-07-18 Mips Technologies, Inc. Instruction prediction based on filtering
US6205537B1 (en) * 1998-07-16 2001-03-20 University Of Rochester Mechanism for dynamically adapting the complexity of a microprocessor
US6314494B1 (en) * 1999-04-15 2001-11-06 Agilent Technologies, Inc. Dynamically size configurable data buffer for data cache and prefetch cache memory
DE69935066D1 (de) * 1999-05-03 2007-03-22 St Microelectronics Sa Befehlsvorausholeinheit
US6490716B1 (en) * 1999-08-20 2002-12-03 Hewlett-Packard Company Automated design of processor instruction units
US6574727B1 (en) 1999-11-04 2003-06-03 International Business Machines Corporation Method and apparatus for instruction sampling for performance monitoring and debug
US6775765B1 (en) 2000-02-07 2004-08-10 Freescale Semiconductor, Inc. Data processing system having instruction folding and method thereof
US6751724B1 (en) 2000-04-19 2004-06-15 Motorola, Inc. Method and apparatus for instruction fetching
US6691220B1 (en) 2000-06-06 2004-02-10 International Business Machines Corporation Multiprocessor speculation mechanism via a barrier speculation flag
US6728873B1 (en) 2000-06-06 2004-04-27 International Business Machines Corporation System and method for providing multiprocessor speculation within a speculative branch path
US7865747B2 (en) * 2000-10-31 2011-01-04 International Business Machines Corporation Adaptive issue queue for reduced power at high performance
US6748522B1 (en) 2000-10-31 2004-06-08 International Business Machines Corporation Performance monitoring based on instruction sampling in a microprocessor
US6832280B2 (en) 2001-08-10 2004-12-14 Freescale Semiconductor, Inc. Data processing system having an adaptive priority controller
US20030105926A1 (en) * 2001-12-03 2003-06-05 International Business Machies Corporation Variable size prefetch cache
US6931494B2 (en) * 2002-09-09 2005-08-16 Broadcom Corporation System and method for directional prefetching
US6895530B2 (en) 2003-01-24 2005-05-17 Freescale Semiconductor, Inc. Method and apparatus for controlling a data processing system during debug
US6925542B2 (en) 2003-03-21 2005-08-02 Freescale Semiconductor, Inc. Memory management in a data processing system
US6963963B2 (en) 2003-03-25 2005-11-08 Freescale Semiconductor, Inc. Multiprocessor system having a shared main memory accessible by all processor units
US7146467B2 (en) * 2003-04-14 2006-12-05 Hewlett-Packard Development Company, L.P. Method of adaptive read cache pre-fetching to increase host read throughput
US6871246B2 (en) 2003-05-07 2005-03-22 Freescale Semiconductor, Inc. Prefetch control in a data processing system
US7139878B2 (en) * 2003-06-20 2006-11-21 Freescale Semiconductor, Inc. Method and apparatus for dynamic prefetch buffer configuration and replacement
US7610466B2 (en) 2003-09-05 2009-10-27 Freescale Semiconductor, Inc. Data processing system using independent memory and register operand size specifiers and method thereof
US7096348B2 (en) 2003-12-15 2006-08-22 Freescale Semiconductor, Inc. Method and apparatus for allocating entries in a branch target buffer
US6976110B2 (en) 2003-12-18 2005-12-13 Freescale Semiconductor, Inc. Method and apparatus for reducing interrupt latency by dynamic buffer sizing
US20050273310A1 (en) 2004-06-03 2005-12-08 Newburn Chris J Enhancements to performance monitoring architecture for critical path-based analysis
US7249223B2 (en) 2004-08-11 2007-07-24 Freescale Semiconductor, Inc. Prefetching in a data processing system
US8001363B2 (en) 2005-04-04 2011-08-16 Globalfoundries Inc. System for speculative branch prediction optimization and method thereof

Also Published As

Publication number Publication date
US20070226462A1 (en) 2007-09-27
EP1999574A2 (en) 2008-12-10
US9304773B2 (en) 2016-04-05
WO2007109395A3 (en) 2008-10-30
EP1999574B1 (en) 2012-04-11
WO2007109395A2 (en) 2007-09-27
KR20080102213A (ko) 2008-11-24
EP1999574A4 (en) 2009-06-03
JP2009530753A (ja) 2009-08-27

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