JP5279323B2 - 半導体層を有する基板の作製方法 - Google Patents

半導体層を有する基板の作製方法 Download PDF

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Publication number
JP5279323B2
JP5279323B2 JP2008102310A JP2008102310A JP5279323B2 JP 5279323 B2 JP5279323 B2 JP 5279323B2 JP 2008102310 A JP2008102310 A JP 2008102310A JP 2008102310 A JP2008102310 A JP 2008102310A JP 5279323 B2 JP5279323 B2 JP 5279323B2
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layer
substrate
glass substrate
single crystal
heat treatment
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JP2008102310A
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Japanese (ja)
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JP2008294417A5 (https=
JP2008294417A (ja
Inventor
舜平 山崎
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008102310A priority Critical patent/JP5279323B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
JP2008102310A 2007-04-27 2008-04-10 半導体層を有する基板の作製方法 Expired - Fee Related JP5279323B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008102310A JP5279323B2 (ja) 2007-04-27 2008-04-10 半導体層を有する基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007120186 2007-04-27
JP2007120186 2007-04-27
JP2008102310A JP5279323B2 (ja) 2007-04-27 2008-04-10 半導体層を有する基板の作製方法

Publications (3)

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JP2008294417A JP2008294417A (ja) 2008-12-04
JP2008294417A5 JP2008294417A5 (https=) 2011-04-14
JP5279323B2 true JP5279323B2 (ja) 2013-09-04

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US (1) US7635617B2 (https=)
JP (1) JP5279323B2 (https=)
KR (1) KR101436115B1 (https=)

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* Cited by examiner, † Cited by third party
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JP2010067815A (ja) * 2008-09-11 2010-03-25 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法

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JP5580010B2 (ja) * 2008-09-05 2014-08-27 株式会社半導体エネルギー研究所 半導体装置の作製方法
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KR101673016B1 (ko) * 2013-08-27 2016-11-07 삼성디스플레이 주식회사 박막봉지 제조장치 및 이를 이용한 표시 장치의 제조방법
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KR102507947B1 (ko) * 2015-10-15 2023-03-09 삼성전자주식회사 케이스 및 이를 포함하는 전자 장치
KR102460564B1 (ko) 2016-02-17 2022-11-01 삼성전자주식회사 반도체 소자
TW202216444A (zh) 2016-08-30 2022-05-01 美商康寧公司 用於片材接合的矽氧烷電漿聚合物
TWI810161B (zh) 2016-08-31 2023-08-01 美商康寧公司 具以可控制式黏結的薄片之製品及製作其之方法
US11637009B2 (en) * 2016-10-07 2023-04-25 Semiconductor Energy Laboratory Co., Ltd. Cleaning method of glass substrate, manufacturing method of semiconductor device, and glass substrate
CN111372772A (zh) 2017-08-18 2020-07-03 康宁股份有限公司 使用聚阳离子聚合物的临时结合
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CN111712758B (zh) 2017-12-15 2023-03-21 成都奕斯伟系统集成电路有限公司 将驱动器ic嵌入lcd显示基板中的系统和方法
CN111566551B (zh) 2018-01-04 2023-06-02 成都奕斯伟系统集成电路有限公司 具有嵌入式ic系统的无边框lcd显示器及其制造方法
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010067815A (ja) * 2008-09-11 2010-03-25 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法

Also Published As

Publication number Publication date
US7635617B2 (en) 2009-12-22
KR20080096372A (ko) 2008-10-30
US20080268618A1 (en) 2008-10-30
JP2008294417A (ja) 2008-12-04
KR101436115B1 (ko) 2014-09-01

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