JP5278782B2 - Manufacturing method of aggregate substrate - Google Patents

Manufacturing method of aggregate substrate Download PDF

Info

Publication number
JP5278782B2
JP5278782B2 JP2011549379A JP2011549379A JP5278782B2 JP 5278782 B2 JP5278782 B2 JP 5278782B2 JP 2011549379 A JP2011549379 A JP 2011549379A JP 2011549379 A JP2011549379 A JP 2011549379A JP 5278782 B2 JP5278782 B2 JP 5278782B2
Authority
JP
Japan
Prior art keywords
substrate
layer
ceramic
shrinkage suppression
suppression layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2011549379A
Other languages
Japanese (ja)
Other versions
JPWO2011152085A1 (en
Inventor
智哉 横山
純一 南條
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2011549379A priority Critical patent/JP5278782B2/en
Publication of JPWO2011152085A1 publication Critical patent/JPWO2011152085A1/en
Application granted granted Critical
Publication of JP5278782B2 publication Critical patent/JP5278782B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B18/00Layered products essentially comprising ceramics, e.g. refractory products
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • CCHEMISTRY; METALLURGY
    • C04CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04BLIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/32Ceramic
    • CCHEMISTRY; METALLURGY
    • C04CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04BLIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/50Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/64Forming laminates or joined articles comprising grooves or cuts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/0909Preformed cutting or breaking line
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material

Description

本発明は、集合基板の製造方法に関し、詳しくは、多層セラミック基板を含む集合基板の製造方法に関する。   The present invention relates to a method for manufacturing an aggregate substrate, and more particularly to a method for manufacturing an aggregate substrate including a multilayer ceramic substrate.

従来、多層セラミック基板に部品を実装したモジュール部品等を製造する方法として、個基板になる部分を含む集合基板に部品を実装した後、集合基板を個基板に分割する工法が知られている。集合基板は、セラミックグリーンシートを積層した積層体を焼成することにより作製される。   2. Description of the Related Art Conventionally, as a method for manufacturing a module component or the like in which components are mounted on a multilayer ceramic substrate, a method of dividing a collective substrate into individual substrates after mounting the components on the collective substrate including a portion that becomes a single substrate is known. The aggregate substrate is produced by firing a laminate in which ceramic green sheets are laminated.

例えば、図7は、集合基板を作製するための積層体111を示す平面図である。積層体111は、セラミックグリーンシート112が積層されている。セラミックグリーンシート112は、中央部116に導電ペースト膜113が形成され、周辺部114に導電ペーストからなる収縮抑制層115が形成されている。導電ペーストとセラミックグリーンシート112の収縮率が異なるので、周辺部に収縮抑制層115を設けることにより、中央部116と周辺部114との収縮の差を小さくすることができ集合基板に歪みが生じないとされている(例えば、特許文献1参照)。   For example, FIG. 7 is a plan view showing a stacked body 111 for producing an aggregate substrate. In the laminated body 111, ceramic green sheets 112 are laminated. In the ceramic green sheet 112, a conductive paste film 113 is formed in the central portion 116, and a shrinkage suppression layer 115 made of a conductive paste is formed in the peripheral portion 114. Since the shrinkage rates of the conductive paste and the ceramic green sheet 112 are different, by providing the shrinkage suppression layer 115 in the peripheral part, the difference in shrinkage between the central part 116 and the peripheral part 114 can be reduced, and the aggregate substrate is distorted. (For example, refer to Patent Document 1).

特開2001−308526号公報JP 2001-308526 A

しかし、図7では、セラミックグリーンシートの外周縁と収縮抑制層との間に間隔Gが設けられている。セラミックグリーンシートの外周縁と収縮抑制層115との間に間隔Gを設けた積層体は、収縮抑制層115とセラミックグリーンシート112との収縮率の差により歪む。そのため、焼成後の積層体の端面にひびが生じたり、焼成前の積層体の表面に形成したブレイク用溝が焼成後に局所的に変形し、ブレイク用溝を起点に基板が割れたり、ひびが発生したりすることがある。焼成後の積層体、すなわち集合基板にひびが発生すると、強度が低下するため、焼成後の部品実装工程や工程間の搬送中の衝撃等によって、集合基板が割れやすくなる。   However, in FIG. 7, a gap G is provided between the outer peripheral edge of the ceramic green sheet and the shrinkage suppression layer. The laminate in which the gap G is provided between the outer peripheral edge of the ceramic green sheet and the shrinkage suppression layer 115 is distorted due to the difference in shrinkage rate between the shrinkage suppression layer 115 and the ceramic green sheet 112. Therefore, cracks are generated on the end face of the laminate after firing, or the break grooves formed on the surface of the laminate before firing are locally deformed after firing, and the substrate is cracked or cracked starting from the break grooves. May occur. If cracks occur in the fired laminate, that is, the collective substrate, the strength decreases, and the collective substrate easily breaks due to a component mounting process after firing, an impact during conveyance between processes, or the like.

本発明は、かかる実情に鑑み、集合基板にひびが発生したり、集合基板の割れが発生したりすることを防ぐことができる集合基板の製造方法を提供しようとするものである。   In view of such a situation, the present invention is intended to provide a method for manufacturing an aggregate substrate that can prevent the aggregate substrate from cracking or the aggregate substrate from being cracked.

本発明は、上記課題を解決するために、以下のように構成した集合基板の製造方法を提供する。   In order to solve the above problems, the present invention provides a method for manufacturing an aggregate substrate configured as follows.

集合基板の製造方法は、(i)未焼成の積層体を準備する第1の工程と、(ii)未焼成の前記積層体を焼成し、焼成が完了した前記積層体により集合基板を形成する第2の工程とを備える。未焼成の前記積層体は、(a)個基板になる部分を含む個基板領域と該個基板領域の周囲を囲む周辺領域とを有し、互いに積層され圧着された複数層の未焼結のセラミック層と、(b)互いに隣接する前記セラミック層の間に配置され、前記セラミック層の外周縁に接するように前記セラミック層の前記周辺領域に形成された収縮抑制層とを備える。未焼成の前記積層体は、前記セラミック層の積層方向両側において外部に露出する主面の少なくとも一方に、個基板になる部分の境界線及びその延長線に沿って、個基板に分割するためのブレイク用溝が形成されている。   The method for manufacturing an aggregate substrate includes (i) a first step of preparing an unsintered laminate, and (ii) firing the unsintered laminate, and forming the aggregate substrate by the laminate after firing is completed. A second step. The unsintered laminate includes (a) an individual substrate region including a portion to be an individual substrate and a peripheral region surrounding the periphery of the individual substrate region. A ceramic layer; and (b) a shrinkage suppression layer that is disposed between the ceramic layers adjacent to each other and is formed in the peripheral region of the ceramic layer so as to be in contact with the outer peripheral edge of the ceramic layer. The unsintered laminate is divided into individual substrates along a boundary line of a portion to be an individual substrate and an extension line thereof on at least one of main surfaces exposed to the outside on both sides in the lamination direction of the ceramic layers. Break grooves are formed.

上記方法により作製された集合基板は、そのセラミック層の積層方向両側の外部に露出する主面間に延在しかつ外部に露出する端面に、収縮抑制層が露出している。   In the aggregate substrate manufactured by the above method, the shrinkage suppression layer is exposed at the end surfaces that are exposed to the outside and exposed to the outside on both sides of the ceramic layer in the stacking direction.

未焼結のセラミック層の外周縁との間に間隔を設けて収縮抑制層を形成すると、間隔が設けられた部分、すなわち収縮抑制層が形成されていない部分は、焼成時の収縮が収縮抑制層によって抑制されない。そのため、積層体は、焼成時に積層体の端面付近で不均一に変形し、積層体の端面にひびが生じたり、ブレイク用溝が積層体の端面付近で局所的に変形したりする。   When a shrinkage suppression layer is formed with a gap between the outer peripheral edge of the unsintered ceramic layer, the shrinkage during firing is suppressed in the part where the gap is provided, that is, the part where the shrinkage suppression layer is not formed. Not suppressed by the layer. Therefore, the laminated body deforms unevenly near the end face of the laminated body at the time of firing, cracks are generated in the end face of the laminated body, and break grooves are locally deformed near the end face of the laminated body.

これに対し、上記方法によれば、未焼結のセラミック層の外周縁に接するように収縮抑制層が形成されているので、セラミックグリーンシート112における間隔Gの部分が存在しなくなる。これにより、焼成時に、積層体の端面付近の不均一な変形を緩和し、あるいは無くして、焼成後の積層体の端面にひびが生じたり、ブレイク用溝が局所的に変形したりすることを防止できる。   On the other hand, according to the above method, since the shrinkage suppression layer is formed so as to be in contact with the outer peripheral edge of the unsintered ceramic layer, the portion of the gap G in the ceramic green sheet 112 does not exist. As a result, during firing, uneven deformation near the end face of the laminated body is alleviated or eliminated, and the end face of the laminated body after firing is cracked, or the break groove is locally deformed. Can be prevented.

記収縮抑制層に隣接する前記セラミック層は磁性体セラミック材料を含む。焼結が完了した前記積層体にめっきを行い、前記集合基板の前記端面にめっき層を形成する第3の工程をさらに備える。 The ceramic layer adjacent the leading SL shrinkage suppression layer comprises a magnetic ceramic material. The method further includes a third step of performing plating on the laminated body that has been sintered and forming a plating layer on the end face of the aggregate substrate.

めっきは、端面に露出した収縮抑制層に付着する。また磁性体セラミック材料を含むセラミック層に付着しやすい。そのため、集合基板の端面に強固に付着するめっき層を容易に形成することができる。   The plating adheres to the shrinkage suppression layer exposed at the end face. Moreover, it is easy to adhere to the ceramic layer containing a magnetic ceramic material. Therefore, a plating layer that adheres firmly to the end face of the aggregate substrate can be easily formed.

めっき層を形成する第3の工程までの間に、集合基板の端面にひびが発生しても、そのひびはめっき層によって補修されるので、ひびを起点とする集合基板の割れが生じにくくなる。また、めっき層は集合基板の端面から剥がれにくいため、めっき層の剥離片の付着によるショートや断線などが生じないようにすることができる。   Even if a crack occurs on the end surface of the collective substrate before the third step of forming the plating layer, the crack is repaired by the plating layer, so that the collective substrate is hardly cracked starting from the crack. . In addition, since the plating layer is difficult to peel off from the end face of the aggregate substrate, it is possible to prevent a short circuit or disconnection due to adhesion of a peeling piece of the plating layer.

好ましくは、前記集合基板を前記ブレイク用溝に沿って分割する前に、前記集合基板の個基板になる部分に部品を実装する第4の工程をさらに備える。   Preferably, the method further includes a fourth step of mounting a component on a portion of the collective substrate that becomes an individual substrate before dividing the collective substrate along the break groove.

集合基板に部品を実装した後に分割することにより、個基板を効率よく形成することができる。   The individual substrates can be efficiently formed by dividing the components after mounting them on the collective substrate.

また、本発明は、以下のように構成された集合基板を提供する。   In addition, the present invention provides a collective substrate configured as follows.

集合基板は、(a)個基板になる部分を含む個基板領域と該個基板領域の周囲を囲む周辺領域とを有し、互いに積層され圧着された複数層のセラミック層と、(b)互いに隣接する前記セラミック層の間に配置され、前記セラミック層の前記周辺領域に形成された収縮抑制層とを備える。集合基板は、積層され圧着された前記セラミック層の、前記セラミック層の積層方向両側において外部に露出する主面の少なくとも一方に、個基板になる部分の境界線及びその延長線に沿って、個基板に分割するためのブレイク用溝が形成されている。集合基板は、積層され圧着された前記セラミック層の前記主面間に延在しかつ外部に露出する端面に、前記収縮抑制層が露出している。めっきが、前記端面に露出した前記収縮抑制層に付着している。 The aggregate substrate has (a) a single substrate region including a portion to be a single substrate and a peripheral region surrounding the periphery of the single substrate region, and a plurality of ceramic layers laminated and bonded together, and (b) each other. A shrinkage suppression layer disposed between the adjacent ceramic layers and formed in the peripheral region of the ceramic layer. The collective substrate is separated along at least one of the main surfaces exposed to the outside on both sides of the ceramic layer in the lamination direction of the laminated and pressure-bonded ceramic layers along a boundary line and an extension line of a portion to be a single substrate. Break grooves for dividing the substrate are formed. In the aggregate substrate, the shrinkage suppression layer is exposed at an end surface extending between the main surfaces of the laminated and pressure-bonded ceramic layers and exposed to the outside. Plating adheres to the shrinkage suppression layer exposed at the end face.

上記構成の集合基板は、未焼結のセラミック層が積層された積層体を焼成することにより作製することができる。焼結が完了した積層体、すなわち集合基板は、ブレイク用溝に沿って分割することにより、個基板に分割することができる。   The aggregate substrate having the above-described configuration can be manufactured by firing a laminate in which an unsintered ceramic layer is laminated. The laminated body after completion of the sintering, that is, the collective substrate can be divided into individual substrates by dividing along the breaking grooves.

収縮抑制層が、未焼結のセラミック層の外周縁に接するように形成された積層体を焼成することにより、集合基板の端面に収縮抑制層が露出するようにできる。この場合、集合基板の端面にひびが生じたり、ブレイク用溝が局所的に変形したりすることを防止できる。   By firing the laminate in which the shrinkage suppression layer is in contact with the outer peripheral edge of the unsintered ceramic layer, the shrinkage suppression layer can be exposed at the end face of the aggregate substrate. In this case, it is possible to prevent the end face of the collective substrate from being cracked and the break groove from being locally deformed.

すなわち、未焼結のセラミック層の外周縁との間に間隔を設けて収縮抑制層を形成すると、間隔が設けられた部分、すなわち収縮抑制層が形成されていない部分は、焼成時の収縮が収縮抑制層によって抑制されない。そのため、積層体は、焼成時に積層体の端面付近で不均一に変形し、積層体の端面にひびが生じたり、ブレイク用溝が積層体の端面付近で局所的に変形したりする。これに対し、未焼結のセラミック層の外周縁に接するように収縮抑制層が形成されていると、焼成時に積層体の端面付近の不均一な変形の発生を緩和し、あるいは無くすことができ、焼成後の積層体、すなわち集合基板の端面にひびが生じたり、ブレイク用溝が局所的に変形したりすることを防止できる。   That is, when the shrinkage suppression layer is formed with a gap between the outer peripheral edge of the unsintered ceramic layer, the portion where the gap is provided, that is, the portion where the shrinkage suppression layer is not formed, is shrunk during firing. It is not suppressed by the shrinkage suppression layer. Therefore, the laminated body deforms unevenly near the end face of the laminated body at the time of firing, cracks are generated in the end face of the laminated body, and break grooves are locally deformed near the end face of the laminated body. On the other hand, if the shrinkage suppression layer is formed so as to be in contact with the outer peripheral edge of the unsintered ceramic layer, it is possible to reduce or eliminate the occurrence of uneven deformation near the end face of the laminate during firing. It is possible to prevent the laminated body after firing, that is, the end face of the collective substrate from cracking and the break grooves from being locally deformed.

本発明によれば、集合基板にひびが発生したり、集合基板の割れが発生したりすることを防ぐことができる。   ADVANTAGE OF THE INVENTION According to this invention, it can prevent that a crack generate | occur | produces in a collective board and a crack of a collective board generate | occur | produces.

集合基板の平面図である。(実施例1)It is a top view of an aggregate substrate. Example 1 図1の線A−Aに沿って切断した断面図である。(実施例1)It is sectional drawing cut | disconnected along line AA of FIG. Example 1 図1の線B−Bに沿って切断した断面図である。(実施例1)It is sectional drawing cut | disconnected along line BB of FIG. Example 1 セラミック層の平面図である。(実施例1)It is a top view of a ceramic layer. Example 1 セラミック層の平面図である。(実施例1)It is a top view of a ceramic layer. Example 1 集合基板の平面図である。(比較例1)It is a top view of an aggregate substrate. (Comparative Example 1) 集合基板の平面図である。(従来例)It is a top view of an aggregate substrate. (Conventional example)

以下、本発明の実施の形態について、図1〜図6を参照しながら説明する。   Embodiments of the present invention will be described below with reference to FIGS.

<実施例1> 実施例1の集合基板10について、図1〜図5を参照しながら説明する。   <Example 1> A collective substrate 10 of Example 1 will be described with reference to FIGS.

図1は、焼結が完了した集合基板10の平面図である。図2は、図1の線A−Aに沿って切断した断面図である。図3は、図1の線B−Bに沿って切断した断面図である。   FIG. 1 is a plan view of an aggregate substrate 10 that has been sintered. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a cross-sectional view taken along line BB in FIG.

図1〜図3に示すように、集合基板10は、個基板になる部分11を含む個基板領域11sと、個基板領域11sの周囲を囲む周辺領域11tを有する。図1では、4×4個の個基板になる部分11を、模式的に示している。   As shown in FIGS. 1 to 3, the collective substrate 10 includes an individual substrate region 11 s including a portion 11 to be an individual substrate, and a peripheral region 11 t surrounding the individual substrate region 11 s. FIG. 1 schematically shows a portion 11 that becomes 4 × 4 individual substrates.

集合基板10の基板本体12の一方主面12aには、個基板領域11sの個基板になる部分11の境界線及びその延長線に沿って、断面V字状のブレイク用溝11x,11yが形成されている。集合基板10の基板本体12の他方主面12bには、ブレイク用溝11x,11yに対向して、断面矩形のブレイク用溝11p,11qが形成されている。集合基板10の基板本体12を、ブレイク用溝11p,11q,11x,11yに沿って、対向するブレイク用溝11pと11x、11qと11yの間で切断することにより、集合基板10の個基板領域11sから個基板を分割することができる。   On one main surface 12a of the substrate body 12 of the collective substrate 10, break grooves 11x and 11y having a V-shaped cross section are formed along the boundary line of the portion 11 to be the individual substrate of the individual substrate region 11s and the extension line thereof. Has been. Break grooves 11p and 11q having a rectangular cross section are formed on the other main surface 12b of the substrate body 12 of the collective substrate 10 so as to face the break grooves 11x and 11y. By cutting the substrate body 12 of the collective substrate 10 along the break grooves 11p, 11q, 11x, and 11y between the opposing break grooves 11p and 11x and 11q and 11y, individual substrate regions of the collective substrate 10 Individual substrates can be divided from 11 s.

図2に示すように、集合基板10の個基板になる部分11は、部品2,4を実装するためのランド電極26a,26b(図1では、図示せず)が基板本体12の一方主面12aに形成され、個基板を他の回路基板等に実装するための端子電極28が基板本体12の他方主面12bに形成されている。なお、個基板に部品が実装されない場合には、ランド電極26a,26bを無くすことができる。   As shown in FIG. 2, land electrode 26 a, 26 b (not shown in FIG. 1) for mounting components 2, 4 is provided on one main surface of substrate main body 12. A terminal electrode 28 is formed on the other main surface 12b of the substrate body 12 so as to be mounted on the other circuit board or the like. If no component is mounted on the individual substrate, the land electrodes 26a and 26b can be eliminated.

図2及び図3に示すように、集合基板10の基板本体12は、順に、第1の非磁性フェライト層16a、第1の磁性層14a、中間非磁性フェライト層16c、第2の磁性層14b、第2の非磁性フェライト層16bが積層されている。第1及び第2の磁性層14a,14bは、例えば、酸化鉄、酸化亜鉛、酸化ニッケル及び酸化銅を主成分とする磁性フェライトと、セラミック材料とを含む。すなわち、第1及び第2の磁性層14a,14bは、磁性体セラミック材料を含む。第1及び第2の非磁性フェライト層16a,16bと中間非磁性フェライト層16cとは、例えば、酸化鉄、酸化亜鉛及び酸化銅を主成分とする非磁性フェライトと、セラミック材料とを含む。各層14a,14b,16a,16b,16cは、1層又は積層された2層以上のセラミック層からなる。   As shown in FIGS. 2 and 3, the substrate body 12 of the collective substrate 10 includes, in order, a first nonmagnetic ferrite layer 16a, a first magnetic layer 14a, an intermediate nonmagnetic ferrite layer 16c, and a second magnetic layer 14b. The second nonmagnetic ferrite layer 16b is laminated. The first and second magnetic layers 14a and 14b include, for example, magnetic ferrite mainly composed of iron oxide, zinc oxide, nickel oxide, and copper oxide, and a ceramic material. That is, the first and second magnetic layers 14a and 14b include a magnetic ceramic material. The first and second nonmagnetic ferrite layers 16a and 16b and the intermediate nonmagnetic ferrite layer 16c include, for example, nonmagnetic ferrite mainly composed of iron oxide, zinc oxide and copper oxide, and a ceramic material. Each layer 14a, 14b, 16a, 16b, 16c consists of one layer or two or more laminated ceramic layers.

図2に示すように、集合基板10は、基板本体12の個基板領域11sの内部に、ビアホール導体24a,24bと、コイル20と、配線導体21とが形成されている。コイル20の一端は、不図示の配線導体により、ビアホール導体24aと接続されている。ビアホール導体24bと24aとが配線導体21により接続されている。   As shown in FIG. 2, in the collective substrate 10, via-hole conductors 24 a and 24 b, a coil 20, and a wiring conductor 21 are formed in the individual substrate region 11 s of the substrate body 12. One end of the coil 20 is connected to the via-hole conductor 24a by a wiring conductor (not shown). Via-hole conductors 24 b and 24 a are connected by a wiring conductor 21.

図2及び図3に示すように、基板本体12の周辺領域11tの内部には、収縮抑制層30,32が形成されている。収縮抑制層30,32は、集合基板10の基板本体12の端面12p,12qに露出している。詳しくは後述するが、ブレイク用溝11p,11q,11x,11yから離れている収縮抑制層30は、個基板領域11sの周囲を取り囲むように連続して形成されている。ブレイク用溝11x,11yの近傍の収縮抑制層32は、収縮抑制層32がブレイク用溝11x,11yに露出しないようにスリット34が形成され、個基板領域11sの周囲を取り囲むように断続的に形成されている。   As shown in FIGS. 2 and 3, shrinkage suppression layers 30 and 32 are formed inside the peripheral region 11 t of the substrate body 12. The shrinkage suppression layers 30 and 32 are exposed on the end faces 12p and 12q of the substrate body 12 of the collective substrate 10. As will be described in detail later, the shrinkage suppression layer 30 separated from the break grooves 11p, 11q, 11x, and 11y is continuously formed so as to surround the periphery of the individual substrate region 11s. The shrinkage suppression layer 32 in the vicinity of the break grooves 11x and 11y is formed with slits 34 so that the shrinkage suppression layer 32 is not exposed to the break grooves 11x and 11y, and intermittently so as to surround the individual substrate region 11s. Is formed.

ビアホール導体24a,24bは、基板本体12のセラミック層を貫通する層間接続導体により形成される。コイル20と配線導体21と収縮抑制層30,32とは、基板本体12のセラミック層に沿って延在する面内接続導体によって形成される。収縮抑制層30,32は、コイル20や配線導体21と同じ材料で形成すると工程が簡単になるが、コイル20や配線導体21とは異なる材料を用いて形成してもよいThe via-hole conductors 24 a and 24 b are formed by interlayer connection conductors that penetrate the ceramic layer of the substrate body 12. The coil 20, the wiring conductor 21, and the shrinkage suppression layers 30 and 32 are formed by in-plane connection conductors that extend along the ceramic layer of the substrate body 12. Shrinkage control layers 30 and 32, but steps can be simplified by forming the same material as the coil 20 and the wiring conductor 21, it may be formed using a material different from that of the coil 20 and the wiring conductor 21.

コイル20は、第1及び第2の磁性層14a,14bと中間非磁性フェライト層16cの内部に形成されている。中間非磁性フェライト層16cがない構成とすることもできるが、第1及び第2の磁性層14a,14bの間に中間非磁性フェライト層16cを形成すると、中間非磁性フェライト層16cがなく磁性層だけにコイルが形成された場合よりも、コイル20の特性を向上(鉄損抑制による電圧変換効率の向上、或いはインダクタンス値の向上など)させることができるので好ましい。   The coil 20 is formed inside the first and second magnetic layers 14a and 14b and the intermediate nonmagnetic ferrite layer 16c. Although the intermediate nonmagnetic ferrite layer 16c may be omitted, if the intermediate nonmagnetic ferrite layer 16c is formed between the first and second magnetic layers 14a and 14b, there is no intermediate nonmagnetic ferrite layer 16c and the magnetic layer It is preferable because the characteristics of the coil 20 can be improved (improvement of voltage conversion efficiency by suppressing iron loss, improvement of inductance value, etc.), compared with the case where the coil is formed only on the other side.

もろくて欠けやすい第1及び第2の磁性層14a,14bは、基板本体12の主面12a,12bに露出しないように第1及び第2の非磁性フェライト層16a,16bに覆われ、保護されている。   The first and second magnetic layers 14a and 14b that are brittle and easily chipped are covered and protected by the first and second nonmagnetic ferrite layers 16a and 16b so as not to be exposed on the main surfaces 12a and 12b of the substrate body 12. ing.

集合基板10は、層間接続導体や面内接続導体が形成された未焼結のセラミックグリーンシートを積層し、焼成することにより、製造することができる。焼成後の基板本体12の厚みは、例えば100〜2000μmである。   The collective substrate 10 can be manufactured by stacking and firing unsintered ceramic green sheets on which interlayer connection conductors and in-plane connection conductors are formed. The thickness of the substrate body 12 after baking is, for example, 100 to 2000 μm.

集合基板10は、周辺領域11tにおいて収縮抑制層30,32が基板本体部12の端面12p,12qまで延在するように形成されているため、基板本体部12の周辺領域11tの厚みが略均一に厚くなることで、強度が向上する。   Since the aggregate substrate 10 is formed such that the shrinkage suppression layers 30 and 32 extend to the end faces 12p and 12q of the substrate body 12 in the peripheral region 11t, the thickness of the peripheral region 11t of the substrate body 12 is substantially uniform. By increasing the thickness, the strength is improved.

収縮抑制層が基板本体部の端面から離れている場合には、基板本体部の端面付近で不均一な焼成収縮によってブレイク用溝の幅が広がり、ブレイク用溝を起点に基板が割れやすくなるが、収縮抑制層30,32が基板本体部12の端面12p,12qまで延在するように形成されていると、焼成時の収縮は、基板本体部12の端面12p,12qまで略均一になるため、ブレイク用溝の幅は一定となり、ブレイク用溝を起点する基板の割れが生じない。   When the shrinkage suppression layer is separated from the end surface of the substrate body, the width of the break groove is widened by non-uniform baking shrinkage near the end surface of the substrate body, and the substrate is likely to crack starting from the break groove. When the shrinkage suppression layers 30 and 32 are formed so as to extend to the end surfaces 12p and 12q of the substrate body 12, the shrinkage during firing becomes substantially uniform up to the end surfaces 12p and 12q of the substrate body 12. The width of the break groove is constant, and the substrate starting from the break groove does not crack.

基板本体12の周辺領域11tにおいて、基板本体12の一方主面12aと他方主面12bの表面には収縮抑制層が配置されない。表面以外の内部には収縮抑制層30,32が配置される。面内接続導体の線膨張係数はセラミック層の線膨張係数より大きいため、焼成後の基板本体12には圧縮応力が残留し、基板強度が向上する。   In the peripheral region 11t of the substrate body 12, no shrinkage suppression layer is disposed on the surfaces of the one main surface 12a and the other main surface 12b of the substrate body 12. Shrinkage suppression layers 30 and 32 are disposed inside the surface other than the surface. Since the linear expansion coefficient of the in-plane connection conductor is larger than the linear expansion coefficient of the ceramic layer, compressive stress remains in the fired substrate body 12 and the substrate strength is improved.

焼成後の積層体の端面には収縮抑制層30,32が突出する。そのため、焼成後の積層体である基板本体12の端面12p,12qに、容易にめっきを形成できる。ハンドリング中の衝撃などによって基板本体12に端面12p,12qに多少のひびができても、そのひびは、めっきによって補修される。   Shrinkage suppression layers 30 and 32 protrude from the end face of the fired laminate. Therefore, plating can be easily formed on the end faces 12p and 12q of the substrate body 12 which is a laminated body after firing. Even if the substrate body 12 has some cracks on the end faces 12p and 12q due to impact during handling, the cracks are repaired by plating.

さらに、端面12p,12qにひびがない場合でも、基板の強度自体がめっきで補強されることで、その後の部品実装工程や工程間の搬送中において基板割れを抑制できる。   Furthermore, even when the end faces 12p and 12q are not cracked, the substrate itself can be reinforced by plating, so that the substrate can be prevented from cracking during the subsequent component mounting process or transfer between processes.

基板本体12の各層を形成するセラミック材料として、比較的低抵抗で電流の流れやすい材料を用いると、めっき時に基板本体12の端面12p,12qに電流が流れやすくなり、基板本体12の端面12p,12qに十分にめっきを形成することができる。   If a material having a relatively low resistance and a current easily flows is used as the ceramic material for forming each layer of the substrate body 12, a current easily flows through the end surfaces 12 p and 12 q of the substrate body 12 during plating. Plating can be formed sufficiently for 12q.

この場合、基板本体12の厚み方向(各層の積層方向)に隣接する収縮抑制層30,32の間の距離が大きくても、基板本体12の端面12p,12qに強固にめっきが付くため、めっき後の部品実装工程や工程間の搬送中における集合基板の割れを、より抑制することができる。また、基板本体12の端面12p,12qに形成させためっき部分が剥がれると、剥離片の付着によりショートや断線などの不良が生じかねないが、このような不具合発生も防止することもできる。   In this case, even if the distance between the shrinkage suppression layers 30 and 32 adjacent to each other in the thickness direction of the substrate body 12 (the stacking direction of each layer) is large, the end surfaces 12p and 12q of the substrate body 12 are strongly plated. It is possible to further suppress the breakage of the collective substrate during the subsequent component mounting process or conveyance between processes. Further, if the plated portions formed on the end faces 12p and 12q of the substrate body 12 are peeled off, a defect such as a short circuit or a disconnection may occur due to the adhesion of the peeled piece, but such a trouble can be prevented.

次に、集合基板10の製造工程について説明する。   Next, the manufacturing process of the collective substrate 10 will be described.

(1)まず、集合基板10の基板本体12のセラミック層の各層を形成するため、セラミック材料粉末を含み、シート状に成形された未焼結のセラミックグリーンシートを準備する。   (1) First, in order to form each layer of the ceramic layers of the substrate body 12 of the collective substrate 10, an unsintered ceramic green sheet containing a ceramic material powder and formed into a sheet shape is prepared.

第1及び第2の磁性層14a,14bになるセラミックグリーンシートには、例えば、酸化鉄、酸化亜鉛、酸化ニッケル及び酸化銅を主成分とする磁性フェライトを添加する。第1及び第2の非磁性フェライト層16a,16bや中間非磁性フェライト層16cになるセラミックグリーンシートには、例えば、酸化鉄、酸化亜鉛及び酸化銅を主成分とする非磁性フェライトを添加する。   For example, magnetic ferrite containing iron oxide, zinc oxide, nickel oxide and copper oxide as main components is added to the ceramic green sheets to be the first and second magnetic layers 14a and 14b. For example, nonmagnetic ferrite containing iron oxide, zinc oxide, and copper oxide as main components is added to the ceramic green sheets that become the first and second nonmagnetic ferrite layers 16a and 16b and the intermediate nonmagnetic ferrite layer 16c.

セラミックグリーンシートには、適宜位置にレーザー加工やパンチング加工等により貫通孔を加工し、この貫通孔に導体ペーストを印刷等により埋め込むことによって、焼成後にビアホール導体となる層間接続導体を形成する。また、セラミックグリーンシートの一方主面に、導体ペーストをスクリーン印刷法やグラビア印刷法等により印刷するか、あるいは所定パターン形状の金属箔を転写する等によって、コイル20、配線導体21、収縮抑制層30,32になる面内接続導体を形成する。   In the ceramic green sheet, through holes are formed at appropriate positions by laser processing, punching processing, or the like, and a conductive paste is embedded in the through holes by printing or the like, thereby forming an interlayer connection conductor that becomes a via hole conductor after firing. Moreover, the coil 20, the wiring conductor 21, and the shrinkage suppression layer are formed by printing a conductive paste on one main surface of the ceramic green sheet by a screen printing method or a gravure printing method or by transferring a metal foil having a predetermined pattern shape. In-plane connection conductors 30 and 32 are formed.

セラミックグリーンシートは、集合基板10よりも大きいものを準備し、積層後に一括して所定サイズに切断する。   A ceramic green sheet larger than the aggregate substrate 10 is prepared, and is cut into a predetermined size all at once after lamination.

図4は、ブレイク用溝11p,11q,11x,11yから離れた層になるセラミックグリーンシート15の平面図である。図4に示すように、セラミックグリーンシート15の一方主面15aには、個基板領域11sの外側に、枠状に連続する収縮抑制層30を形成する。収縮抑制層30は、周辺領域11tよりも外側の耳部15zにはみ出るように形成する。   FIG. 4 is a plan view of the ceramic green sheet 15 that is separated from the breaking grooves 11p, 11q, 11x, and 11y. As shown in FIG. 4, a shrinkage suppression layer 30 that is continuous in a frame shape is formed on one main surface 15 a of the ceramic green sheet 15 outside the individual substrate region 11 s. The shrinkage suppression layer 30 is formed so as to protrude from the ear portion 15z outside the peripheral region 11t.

図5は、ブレイク用溝11x,11yの近傍の収縮抑制層32が形成されたセラミックグリーンシート13の平面図である。図5に示すように、セラミックグリーンシート13の一方主面13aには、個基板領域11sの外側に、個基板領域11sの周囲を取り囲むように枠状の収縮抑制層32を形成するが、収縮抑制層32にはスリット34を形成する。このスリット34の中心付近には、図3に示すように、ブレイク用溝11x,11yが形成される。すなわち、収縮抑制層32がブレイク用溝11x,11yに露出しないように、ブレイク用溝11x,11yの近傍領域にスリット34を形成する。   FIG. 5 is a plan view of the ceramic green sheet 13 on which the shrinkage suppression layer 32 in the vicinity of the breaking grooves 11x and 11y is formed. As shown in FIG. 5, a frame-like shrinkage suppression layer 32 is formed on one main surface 13a of the ceramic green sheet 13 outside the individual substrate region 11s so as to surround the individual substrate region 11s. A slit 34 is formed in the suppression layer 32. Break grooves 11x and 11y are formed near the center of the slit 34 as shown in FIG. That is, the slits 34 are formed in the vicinity of the break grooves 11x and 11y so that the shrinkage suppression layer 32 is not exposed to the break grooves 11x and 11y.

図示を省略するが、ブレイク用溝11p,11qの近傍の収縮抑制層32が形成されたセラミックグリーンシート13の平面図も図5と同様である。異なる点は、収縮抑制層32がブレイク用溝11p,11qに露出しないように、ブレイク用溝11p,11qの近傍領域にスリット35を形成することである。スリット35の幅はブレイク用溝11p,11qの幅より大きくする。   Although not shown, the plan view of the ceramic green sheet 13 on which the shrinkage suppression layer 32 in the vicinity of the breaking grooves 11p and 11q is formed is the same as that in FIG. A different point is that a slit 35 is formed in a region near the breaking grooves 11p and 11q so that the shrinkage suppression layer 32 is not exposed to the breaking grooves 11p and 11q. The width of the slit 35 is made larger than the width of the break grooves 11p and 11q.

(2)次いで、基板本体12の各層を形成する未焼結のセラミックグリーンシートを、所定の順序で積層した後、積層方向に比較的小さい圧力を加え、仮圧着体を形成する。   (2) Next, after unsintered ceramic green sheets forming each layer of the substrate body 12 are laminated in a predetermined order, a relatively small pressure is applied in the laminating direction to form a temporary pressure bonded body.

(3)次いで、仮圧着体の周囲を切断してセラミックグリーンシートの耳部を除去し、集合基板10になる部分11s,11tのみを含む積層体を形成する。このとき、積層体の端面に収縮抑制層30,32が露出するようになる。   (3) Next, the periphery of the temporary press-bonded body is cut to remove the ear portion of the ceramic green sheet, and a laminated body including only the portions 11s and 11t to be the aggregate substrate 10 is formed. At this time, the shrinkage suppression layers 30 and 32 are exposed at the end face of the laminate.

すなわち、図4に示したセラミックグリーンシート15は、集合基板10になる部分11s,11tと耳部15zとの境界線15x,15yに沿って切断され、収縮抑制層30は境界線15x,15yに沿って切断される。これにより、図2及び図3に示すように、収縮抑制層30の外周縁30x,30yが、集合基板10の端面12p,12qに連続して露出する。このように収縮抑制層30の外周縁30x,30yが集合基板10の端面12p,12qに全周に渡って連続して露出すると、焼成時の収縮による歪みを均一に抑制することができる。   That is, the ceramic green sheet 15 shown in FIG. 4 is cut along the boundary lines 15x and 15y between the portions 11s and 11t that become the collective substrate 10 and the ear part 15z, and the shrinkage suppression layer 30 is cut along the boundary lines 15x and 15y. Cut along. Thereby, as shown in FIGS. 2 and 3, the outer peripheral edges 30 x and 30 y of the shrinkage suppression layer 30 are continuously exposed on the end faces 12 p and 12 q of the collective substrate 10. As described above, when the outer peripheral edges 30x and 30y of the shrinkage suppression layer 30 are continuously exposed on the end faces 12p and 12q of the collective substrate 10 over the entire circumference, distortion due to shrinkage during firing can be suppressed uniformly.

図5に示したセラミックグリーンシート13は、集合基板10になる部分11s,11tと耳部13zとの境界線13x,13yに沿って切断され、収縮抑制層32は境界線13x,13yに沿って切断される。これにより、図2及び図3に示すように、収縮抑制層32の外周縁32x,32yが、集合基板10の端面12p,12qに間欠的に露出する。収縮抑制層32は、焼成時の収縮による歪みを略均一に抑制することができる。   The ceramic green sheet 13 shown in FIG. 5 is cut along the boundary lines 13x and 13y between the portions 11s and 11t to be the aggregate substrate 10 and the ears 13z, and the shrinkage suppression layer 32 is along the boundary lines 13x and 13y. Disconnected. Thereby, as shown in FIGS. 2 and 3, the outer peripheral edges 32 x and 32 y of the shrinkage suppression layer 32 are intermittently exposed to the end faces 12 p and 12 q of the collective substrate 10. The shrinkage suppression layer 32 can suppress distortion due to shrinkage during firing substantially uniformly.

(4)次いで、積層体を焼成する。焼成により、基板本体12の各層を形成するセラミックグリーンシートに含まれるセラミック材料粉末を焼結させる。   (4) Next, the laminate is fired. By firing, the ceramic material powder contained in the ceramic green sheet forming each layer of the substrate body 12 is sintered.

(5)次いで、焼成済みの積層体、すなわち基板本体12を取り出し、必要に応じて、基板本体12の主面12a,12bに形成されたランド電極26a,26bと端子電極28a,28bにめっきを行う。   (5) Next, the fired laminate, that is, the substrate body 12 is taken out, and if necessary, the land electrodes 26a and 26b and the terminal electrodes 28a and 28b formed on the main surfaces 12a and 12b of the substrate body 12 are plated. Do.

このとき、集合基板10の基板本体12の端面12p,12qに、めっきを形成してもよい。集合基板10の基板本体12の端面12p,12qには、磁性層14a,14bと収縮抑制層30,32とが露出しているため、めっきが強固に付着する。   At this time, plating may be formed on the end faces 12p and 12q of the substrate body 12 of the collective substrate 10. Since the magnetic layers 14a and 14b and the shrinkage suppression layers 30 and 32 are exposed on the end faces 12p and 12q of the substrate body 12 of the aggregate substrate 10, the plating adheres firmly.

(6)以上の工程に完成した集合基板10は、ランド電極26a,26bに表面実装部品4やICチップ2などの部品を実装し、モジュール化する。そして、ブレイク用溝11p,11q,11x,11yに沿って切断し、個基板に分割することで、集合基板10からモジュール部品を作製することができる。   (6) The collective substrate 10 completed through the above steps is mounted on the land electrodes 26a and 26b by mounting components such as the surface mount component 4 and the IC chip 2 into a module. Then, by cutting along the break grooves 11p, 11q, 11x, and 11y and dividing into individual substrates, a module component can be manufactured from the collective substrate 10.

<比較例1> 図6は、比較例1の集合基板の基板本体12xの平面図である。図6は、基板本体12xの主面に形成されたブレイク用溝11x,11yのみを図示し、ランド電極や端子電極の図示を省略している。   Comparative Example 1 FIG. 6 is a plan view of the substrate body 12x of the collective substrate of Comparative Example 1. FIG. FIG. 6 illustrates only the break grooves 11x and 11y formed on the main surface of the substrate body 12x, and omits illustration of land electrodes and terminal electrodes.

比較例1の集合基板12xは、基板本体12xの周辺領域に形成された収縮抑制層が、実施例1とは異なり、基板本体12xの端面12p,12qに露出していない。すなわち、基板本体12xになる未焼成の積層体において、セラミックグリーンシートの外周縁と収縮抑制層との間には間隔が設けられている。そのため、積層体の端面付近において焼成時の収縮が収縮抑制層によって抑制されないため、図6に示すように、ブレイク用溝11x,11yの幅が、基板本体12xの端面12p,12q付近で局所的に広がり、基板割れの原因となる。   Unlike the first embodiment, in the aggregate substrate 12x of Comparative Example 1, the shrinkage suppression layer formed in the peripheral region of the substrate body 12x is not exposed on the end faces 12p and 12q of the substrate body 12x. That is, in the unfired laminated body that becomes the substrate body 12x, a gap is provided between the outer peripheral edge of the ceramic green sheet and the shrinkage suppression layer. Therefore, since shrinkage during firing is not suppressed by the shrinkage suppression layer in the vicinity of the end face of the laminate, as shown in FIG. 6, the width of the break grooves 11x and 11y is locally near the end faces 12p and 12q of the substrate body 12x. Spreads and causes cracking of the substrate.

これに対して、実施例1では、基板本体12の端面12p,12qに露出するように収縮抑制層30,32が形成されおり、基板本体12の端面12p,12q付近は、それよりも内側の部分と同様に、焼成時の収縮が収縮抑制層30,32によって抑制される。そのため、図1に示すように、ブレイク用溝11x,11yは、基板本体12の端面12p,12q付近で局所的に広がることなく形成されるので、基板割れが生じない。   On the other hand, in Example 1, the shrinkage | contraction suppression layers 30 and 32 are formed so that it may be exposed to the end surfaces 12p and 12q of the board | substrate body 12, and the end surfaces 12p and 12q vicinity of the board | substrate body 12 is inner side than it. Similar to the portion, shrinkage during firing is suppressed by the shrinkage suppression layers 30 and 32. Therefore, as shown in FIG. 1, since the break grooves 11x and 11y are formed without locally spreading in the vicinity of the end faces 12p and 12q of the substrate body 12, no substrate cracking occurs.

<作製例> 焼成後のサイズが約112×112mm、焼成後の厚みが450〜500μm、基板厚の40〜50%の深さのブレイク用溝が形成された実施例1の構成の集合基板の基板本体の端面をめっきで補強した場合、焼成/めっき工程以降の部品実装工程や工程間の搬送中に、基板本体の周辺領域の構成が原因であるひびや基板割れが一切発生しなかった。これに対し、収縮抑制層が基板本体部の端面から離れている比較例1の構成の集合基板の場合は、焼成時にブレイク用溝を起点とする基板割れや、基板割れには至らないひびが、数〜10%程度発生した。   <Manufacturing Example> The aggregate substrate having the configuration of Example 1 in which the size after baking is about 112 × 112 mm, the thickness after baking is 450 to 500 μm, and the groove for break having a depth of 40 to 50% of the substrate thickness is formed. When the end face of the board body was reinforced by plating, no cracks or board cracks were caused due to the configuration of the peripheral area of the board body during the component mounting process after the firing / plating process or during the transfer between the processes. On the other hand, in the case of the aggregate substrate having the configuration of Comparative Example 1 in which the shrinkage suppression layer is separated from the end surface of the substrate body, there are substrate cracks starting from the break grooves during firing, and cracks that do not cause substrate cracks. About several to 10%.

<まとめ> 以上のように、集合基板10の基板本体12の周辺領域11tの内部に収縮抑制層30,32を形成し、収縮抑制層30,32が集合基板10の基板本体12の端面12p,12qに露出するように構成することにより、集合基板10にひびが発生したり、集合基板10の割れが発生したりすることを防ぐことができる。   <Summary> As described above, the shrinkage suppression layers 30 and 32 are formed inside the peripheral region 11t of the substrate body 12 of the collective substrate 10, and the shrinkage suppression layers 30 and 32 are the end faces 12p of the substrate body 12 of the collective substrate 10. By being configured to be exposed to 12q, it is possible to prevent the aggregate substrate 10 from being cracked or the aggregate substrate 10 from being cracked.

なお、本発明は、上記実施の形態に限定されるものではなく、種々変更を加えて実施することが可能である。   The present invention is not limited to the above embodiment, and can be implemented with various modifications.

例えば、基板本体の各層は、磁性フェライトや非磁性フェライトを含まないセラミック層であってもよい。   For example, each layer of the substrate body may be a ceramic layer that does not include magnetic ferrite or nonmagnetic ferrite.

10 集合基板
11 個基板になる部分
11s 個基板領域
11t 周辺領域
11p,11q,11x,11y ブレイク用溝
12 基板本体
12a,12b 主面
12p,12q 端面
14a,14b 磁性層
16a,16b,16c 非磁性フェライト層
20 コイル
21 配線導体
24a,24b ビアホール導体
26a,26b ランド電極
28a,28b 端子電極
30,32 収縮抑制層
34,35 スリット
10 collective substrate 11 part to become 11 substrate 11s substrate region 11t peripheral region 11p, 11q, 11x, 11y break groove 12 substrate body 12a, 12b main surface 12p, 12q end surface 14a, 14b magnetic layer 16a, 16b, 16c non-magnetic Ferrite layer 20 Coil 21 Wiring conductor 24a, 24b Via hole conductor 26a, 26b Land electrode 28a, 28b Terminal electrode 30, 32 Shrinkage suppression layer 34, 35 Slit

Claims (3)

個基板になる部分を含む個基板領域と該個基板領域の周囲を囲む周辺領域とを有し、互いに積層され圧着された複数層の未焼結のセラミック層と、
互いに隣接する前記セラミック層の間に配置され、前記セラミック層の外周縁に接するように前記セラミック層の前記周辺領域に形成された収縮抑制層と、
を備え、
前記収縮抑制層に隣接する前記セラミック層は磁性体セラミック材料を含み、
前記セラミック層の積層方向両側において外部に露出する主面の少なくとも一方に、個基板になる部分の境界線及びその延長線に沿って、個基板に分割するためのブレイク用溝が形成された、
未焼成の積層体を準備する第1の工程と、
未焼成の前記積層体を焼成し、焼成が完了した前記積層体により集合基板を形成する第2の工程と、
焼結が完了した前記積層体にめっきを行い、前記集合基板の前記端面にメッキ層を形成する第3の工程を備えたことを特徴とする、集合基板の製造方法。
A plurality of unsintered ceramic layers having a single substrate region including a portion to be a single substrate and a peripheral region surrounding the periphery of the single substrate region, and being laminated and pressure-bonded to each other;
A shrinkage suppression layer disposed between the ceramic layers adjacent to each other and formed in the peripheral region of the ceramic layer so as to be in contact with an outer peripheral edge of the ceramic layer;
With
The ceramic layer adjacent to the shrinkage suppression layer includes a magnetic ceramic material,
Break grooves for dividing into individual substrates are formed along at least one of the main surfaces exposed to the outside on both sides in the stacking direction of the ceramic layers, along the boundary line of the portion to be the individual substrate and its extension line,
A first step of preparing an unfired laminate;
A second step of firing the unfired laminate and forming a collective substrate with the laminate after firing;
Perform plating the laminate sintering is completed, the third step you characterized in that example Bei a current focus substrate manufacturing method of forming a plated layer on the end surface of the collective substrate.
前記集合基板を前記ブレイク用溝に沿って分割する前に、前記集合基板の個基板になる部分に部品を実装する第4の工程をさらに備えたことを特徴とする、請求項1に記載の集合基板の製造方法。 2. The method according to claim 1, further comprising a fourth step of mounting a component on a portion of the aggregate substrate that becomes an individual substrate before dividing the aggregate substrate along the break groove. A method for manufacturing an aggregate substrate. 個基板になる部分を含む個基板領域と該個基板領域の周囲を囲む周辺領域とを有し、互いに積層され圧着された複数層のセラミック層と、
互いに隣接する前記セラミック層の間に配置され、前記セラミック層の前記周辺領域に形成された収縮抑制層と、
を備え、
積層され圧着された前記セラミック層の、前記セラミック層の積層方向両側において外部に露出する主面の少なくとも一方に、個基板になる部分の境界線及びその延長線に沿って、個基板に分割するためのブレイク用溝が形成され、
積層され圧着された前記セラミック層の前記主面間に延在しかつ外部に露出する端面に、前記収縮抑制層が露出し
めっきが、前記端面に露出した前記収縮抑制層に付着していることを特徴とする、集合基板。
A plurality of ceramic layers having a single substrate region including a portion to be a single substrate and a peripheral region surrounding the periphery of the single substrate region, and laminated and pressure-bonded to each other;
A shrinkage suppression layer disposed between the ceramic layers adjacent to each other and formed in the peripheral region of the ceramic layer;
With
The laminated ceramic layers are divided into individual substrates along at least one of the main surfaces exposed to the outside on both sides in the lamination direction of the ceramic layers, along the boundary line of the portion to be an individual substrate and its extension line. Break groove for forming,
The shrinkage suppression layer is exposed at an end surface that extends between the main surfaces of the laminated and pressure-bonded ceramic layers and is exposed to the outside ,
The collective substrate , wherein the plating adheres to the shrinkage suppression layer exposed on the end face .
JP2011549379A 2010-06-04 2011-02-15 Manufacturing method of aggregate substrate Active JP5278782B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011549379A JP5278782B2 (en) 2010-06-04 2011-02-15 Manufacturing method of aggregate substrate

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2010129473 2010-06-04
JP2010129473 2010-06-04
JP2011549379A JP5278782B2 (en) 2010-06-04 2011-02-15 Manufacturing method of aggregate substrate
PCT/JP2011/053140 WO2011152085A1 (en) 2010-06-04 2011-02-15 Method for producing integrated substrate

Publications (2)

Publication Number Publication Date
JPWO2011152085A1 JPWO2011152085A1 (en) 2013-07-25
JP5278782B2 true JP5278782B2 (en) 2013-09-04

Family

ID=45066474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011549379A Active JP5278782B2 (en) 2010-06-04 2011-02-15 Manufacturing method of aggregate substrate

Country Status (2)

Country Link
JP (1) JP5278782B2 (en)
WO (1) WO2011152085A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012227306A (en) * 2011-04-19 2012-11-15 Ngk Insulators Ltd Manufacturing method of ceramic substrate
JP6114102B2 (en) * 2013-04-26 2017-04-12 京セラ株式会社 Multi-wiring board
KR102281459B1 (en) * 2014-11-05 2021-07-27 삼성전기주식회사 Printed circuit board and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001308526A (en) * 2000-04-18 2001-11-02 Murata Mfg Co Ltd Method for manufacturing multilayered ceramic substrate and multilayered assembled substrate
JP2004071852A (en) * 2002-08-07 2004-03-04 Hitachi Metals Ltd Multilayer substrate
JP2006066652A (en) * 2004-08-26 2006-03-09 Kyocera Corp Multiple pattern wiring substrate
JP2008186967A (en) * 2007-01-30 2008-08-14 Ngk Spark Plug Co Ltd Multiple-piece taking board

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09181443A (en) * 1995-12-25 1997-07-11 Murata Mfg Co Ltd Electronic component manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001308526A (en) * 2000-04-18 2001-11-02 Murata Mfg Co Ltd Method for manufacturing multilayered ceramic substrate and multilayered assembled substrate
JP2004071852A (en) * 2002-08-07 2004-03-04 Hitachi Metals Ltd Multilayer substrate
JP2006066652A (en) * 2004-08-26 2006-03-09 Kyocera Corp Multiple pattern wiring substrate
JP2008186967A (en) * 2007-01-30 2008-08-14 Ngk Spark Plug Co Ltd Multiple-piece taking board

Also Published As

Publication number Publication date
JPWO2011152085A1 (en) 2013-07-25
WO2011152085A1 (en) 2011-12-08

Similar Documents

Publication Publication Date Title
JP5921074B2 (en) Manufacturing method of laminated substrate
JP5196038B2 (en) Coil built-in board
TWI623000B (en) Laminated coil parts
KR101541505B1 (en) Multilayer ceramic electronic component
JP5621573B2 (en) Coil built-in board
JP2012094820A (en) Multilayer ceramic electronic component
JP2006278556A (en) Multilayer ceramic electronic component
JP2012227198A (en) Multilayer ceramic capacitor
WO2018159481A1 (en) Layered electronic component and method for manufacturing layered electronic component
JP4788544B2 (en) Multilayer ceramic substrate and manufacturing method thereof
JP5278782B2 (en) Manufacturing method of aggregate substrate
WO2011148678A1 (en) Lc co-sintered substrate and method for producing same
CN104981113B (en) The processing method and golden finger circuit board of circuit edge connector
JP2005294486A (en) Laminated electronic component
JP2001251024A (en) Multilayer aggregation substrate and method for manufacturing multilayer ceramic part
JP2012227233A (en) Multilayer electronic component and manufacturing method therefor
JP6195085B2 (en) Laminated electronic components
WO2018159482A1 (en) Layered electronic component and method for manufacturing layered electronic component
JP5935506B2 (en) Multilayer substrate and manufacturing method thereof
JP4272183B2 (en) Multilayer electronic components
JP2007035715A (en) Method of manufacturing multilayer electronic component
JP2012089818A (en) Laminate type ceramic electronic component manufacturing method
JP2009099699A (en) Method of manufacturing electronic component
JPWO2016084783A1 (en) Electronic component manufacturing method, electronic component and electronic device
JP2012109355A (en) Multilayer ferrite substrate and method for manufacturing electronic component

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130425

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130508

R150 Certificate of patent or registration of utility model

Ref document number: 5278782

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150