JP5260755B2 - 半導体チップのパッケージおよびこの製造方法 - Google Patents
半導体チップのパッケージおよびこの製造方法 Download PDFInfo
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- JP5260755B2 JP5260755B2 JP2011541272A JP2011541272A JP5260755B2 JP 5260755 B2 JP5260755 B2 JP 5260755B2 JP 2011541272 A JP2011541272 A JP 2011541272A JP 2011541272 A JP2011541272 A JP 2011541272A JP 5260755 B2 JP5260755 B2 JP 5260755B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Fuses (AREA)
Description
Claims (15)
- チップパッケージ(1)であって、
はんだボール状に形成されている外部電源接続部(VBAT)と、
はんだボール状に形成されている内部電源接続部(VDD)と、
前記内部電源接続部(VDD)と接続された第1の接続ポイント(5)、及び前記外部電源接続部(VBAT)と接続された第2の接続ポイント(6)を有する半導体基板(4)と、
前記チップパッケージ(1)内に配置され、前記内部電源接続部(VDD)および前記外部電源接続部(VBAT)を電気的に接続するヒューズ(3)と、
前記半導体基板(4)上に設けられ、前記第1の接続ポイント(5)を介して前記外部電源接続部(VBAT)に供給される電源電圧の給電を受けるために前記内部電源接続部(VDD)と接続された集積回路(2)と、を備え、
前記集積回路(2)と前記外部電源接続部(VBAT)の間には、前記ヒューズ(3)を除いて、電気的接続が存在しないようになっていることを特徴とするチップパッケージ。 - 前記ヒューズ(3)は、前記集積回路(2)の外側に配置されることを特徴とする請求項1に記載のチップパッケージ。
- 前記外部電源接続部(VBAT)は、前記チップパッケージ(1)の作動中に前記電源電圧が印可されることを特徴とする請求項1または2に記載のチップパッケージ。
- 前記ヒューズ(3)の破壊により、前記集積回路(2)への電源電圧の供給が遮断されることを特徴とする請求項1乃至3に記載のチップパッケージ。
- 電気接続部(11)を介して外部に設けられた電気負荷である回路(10)に接続され、前記回路(10)の障害状態に応じて前記ヒューズ(3)が切断されると前記集積回路(2)への電源電圧の供給が遮断されることを特徴とする請求項4に記載のチップパッケージ。
- ウエハレベルチップサイズパッケージ、ボールグリッドアレイ(BGA)、またはピングリッドアレイ(PGA)として構成されていることを特徴とする請求項1乃至5のいずれかに記載のチップパッケージ。
- 前記集積回路(2)上に、前記外部電源接続部(VBAT)、前記内部電源接続部(VDD)および前記ヒューズ(3)を含む再配線層(7)が形成されていることを特徴とする請求項1乃至3のいずれかに記載のチップパッケージ。
- 前記ヒューズ(3)は、前記再配線層(7)内において、前記外部電源接続部(VBAT)と前記内部電源接続部(VDD)とを電気的に接続する長手の金属層として形成されることを特徴とする請求項7に記載のチップパッケージ。
- 前記長手金属層であるヒューズ(3)は、少なくとも1箇所(31)で、幅が狭まっていることを特徴とする請求項8に記載のチップパッケージ。
- 前記長手金属層であるヒューズ(3)は、チタン/アルミニウム合金、アルミニウムおよび銅を含む導電性金属材料の少なくとも1つからなることを特徴とする請求項8または9に記載のチップパッケージ。
- 前記外部電源接続部(VBAT)および前記内部電源接続部(VDD)を含むハウジング(8)を備え、前記外部電源接続部(VBAT)は、ボンディングワイヤとしての前記ヒューズ(3)を介して、前記第2の接続ポイント(6)と接続されるようになっていることを特徴とする請求項1に記載のチップパッケージ。
- 参照電源接続部(VSS)を備え、かつ前記参照電源接続部(VSS)と前記内部電源接続部(VDD)の間に蓄電装置(9)が設けられており、前記蓄電装置(9)には、前記内部電源接続部(VDD)に印加される電源電圧の安定化のために電荷が蓄積されるようになっていることを特徴とする請求項1乃至11のいずれかに記載のチップパッケージ。
- はんだボール状に形成された外部電源接続部(VBAT)および内部電源接続部(VDD)を備えるチップパッケージ(1)を製造するチップパッケージの製造方法であって、
前記内部電源接続部(VDD)と接続された第1の接続ポイント(5)と、前記外部電源接続部(VBAT)と接続された第2の接続ポイント(6)とを備えた半導体基板(4)上に集積回路(2)を製造する工程と、
前記内部電源接続部(VDD)と前記外部電源接続部(VBAT)を電気的に接続するヒューズ(3)を前記チップパッケージ(1)内に設ける工程と、
前記集積回路(2)が前記外部電源接続部(VBAT)に供給される電源電圧の給電を受けうるように、前記集積回路(2)を前記内部電源接続部(VDD)と接続する工程と、を含み、
前記集積回路(2)と前記外部電源接続部(VBAT)の間には、前記ヒューズ(3)を除いて、電気的接続が存在させないことを特徴とする製造方法。 - 前記チップパッケージ(1)と前記ヒューズ(3)を製造するために、前記外部電源接続部(VBAT)、前記内部電源接続部(VDD)および前記ヒューズ(3)を含む再配線層(7)を、前記集積回路(2)上に形成する工程を含むことを特徴とする請求項13に記載の製造方法。
- 前記チップパッケージ(1)を製造するために、前記外部電源接続部(VBAT)、前記内部電源接続部(VDD)、およびボンディングワイヤとしての前記ヒューズ(3)を含むハウジング(8)を製造する工程を含むことを特徴とする請求項13または14に記載の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102008064428.5 | 2008-12-22 | ||
DE102008064428.5A DE102008064428B4 (de) | 2008-12-22 | 2008-12-22 | Chipaufbau und Verfahren zur Herstellung eines Chipaufbaus |
PCT/EP2009/065652 WO2010072492A1 (de) | 2008-12-22 | 2009-11-23 | Chipaufbau mit eingebauter sicherung und verfahren zu seiner herstellung |
Publications (2)
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JP2012513078A JP2012513078A (ja) | 2012-06-07 |
JP5260755B2 true JP5260755B2 (ja) | 2013-08-14 |
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JP2011541272A Expired - Fee Related JP5260755B2 (ja) | 2008-12-22 | 2009-11-23 | 半導体チップのパッケージおよびこの製造方法 |
Country Status (4)
Country | Link |
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US (1) | US8525331B2 (ja) |
JP (1) | JP5260755B2 (ja) |
DE (1) | DE102008064428B4 (ja) |
WO (1) | WO2010072492A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US9548283B2 (en) * | 2012-07-05 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package redistribution layer structure and method of forming same |
KR101936039B1 (ko) | 2012-10-30 | 2019-01-08 | 삼성전자 주식회사 | 반도체 장치 |
US8907480B2 (en) * | 2013-03-14 | 2014-12-09 | Intel Mobile Communications GmbH | Chip arrangements |
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JPS6214935U (ja) * | 1985-07-09 | 1987-01-29 | ||
JPS6214935A (ja) | 1985-07-13 | 1987-01-23 | Sumitomo Metal Ind Ltd | 溶融スラグ造粒装置 |
JPH01295440A (ja) | 1988-05-24 | 1989-11-29 | Nissan Motor Co Ltd | 半導体装置 |
US5021861A (en) * | 1990-05-23 | 1991-06-04 | North Carolina State University | Integrated circuit power device with automatic removal of defective devices and method of fabricating same |
JPH06139915A (ja) | 1992-10-23 | 1994-05-20 | Rohm Co Ltd | 過電圧過電流に対する保護装置 |
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JP3855088B2 (ja) | 1998-09-30 | 2006-12-06 | 大東通信機株式会社 | 突入電流防止装置、ヒューズ装置およびスイッチング装置 |
JP2000311959A (ja) * | 1999-04-27 | 2000-11-07 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
JP3737673B2 (ja) * | 2000-05-23 | 2006-01-18 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2002025790A (ja) * | 2000-07-12 | 2002-01-25 | Koito Mfg Co Ltd | 放電灯点灯回路 |
US7005727B2 (en) | 2001-12-28 | 2006-02-28 | Intel Corporation | Low cost programmable CPU package/substrate |
DE10334433B4 (de) * | 2003-07-28 | 2009-10-22 | Infineon Technologies Ag | Vorrichtung zur Unterbrechung des Stromflusses zu einem oder von einem Halbleiterkörper eines Halbleiterbauelements |
DE10344391A1 (de) * | 2003-09-25 | 2005-05-12 | Infineon Technologies Ag | Anordnung zur Verbindung in integrierten MOS-Strukturen |
DE102005024347B8 (de) | 2005-05-27 | 2010-07-08 | Infineon Technologies Ag | Elektrisches Bauteil mit abgesichertem Stromzuführungsanschluss |
US7435627B2 (en) * | 2005-08-11 | 2008-10-14 | International Business Machines Corporation | Techniques for providing decoupling capacitance |
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KR100886710B1 (ko) * | 2007-07-27 | 2009-03-04 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이의 제조 방법 |
KR100905779B1 (ko) * | 2007-08-20 | 2009-07-02 | 주식회사 하이닉스반도체 | 반도체 패키지 |
JP4840305B2 (ja) | 2007-09-14 | 2011-12-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4166268B1 (ja) | 2008-02-08 | 2008-10-15 | 義久 石黒 | 電源停止型コンピュータシステム |
US8018043B2 (en) * | 2008-03-10 | 2011-09-13 | Hynix Semiconductor Inc. | Semiconductor package having side walls and method for manufacturing the same |
-
2008
- 2008-12-22 DE DE102008064428.5A patent/DE102008064428B4/de not_active Expired - Fee Related
-
2009
- 2009-11-23 US US13/141,687 patent/US8525331B2/en not_active Expired - Fee Related
- 2009-11-23 WO PCT/EP2009/065652 patent/WO2010072492A1/de active Application Filing
- 2009-11-23 JP JP2011541272A patent/JP5260755B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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US8525331B2 (en) | 2013-09-03 |
DE102008064428A1 (de) | 2010-07-08 |
JP2012513078A (ja) | 2012-06-07 |
WO2010072492A1 (de) | 2010-07-01 |
DE102008064428B4 (de) | 2016-02-25 |
US20120104605A1 (en) | 2012-05-03 |
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