JP5258193B2 - フローティングゲート型メモリアレイの製造方法 - Google Patents
フローティングゲート型メモリアレイの製造方法 Download PDFInfo
- Publication number
- JP5258193B2 JP5258193B2 JP2006509973A JP2006509973A JP5258193B2 JP 5258193 B2 JP5258193 B2 JP 5258193B2 JP 2006509973 A JP2006509973 A JP 2006509973A JP 2006509973 A JP2006509973 A JP 2006509973A JP 5258193 B2 JP5258193 B2 JP 5258193B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- source region
- floating gate
- type dopant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000002019 doping agent Substances 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 22
- 230000000694 effects Effects 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 5
- 125000001475 halogen functional group Chemical group 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
Claims (4)
- フローティングゲート型メモリアレイの製造方法であって、
第1のソース領域(116,216,316)と第2のソース領域(118,218)の間に設けられ、基板(258,358)のサイドウォール(150,250)を規定するトレンチ(128,228)を露出させるために、前記基板(258,358)に設けられた分離領域(110)から誘電体を除去する工程(404)と、
N+型領域(252,352)を形成するN型ドーパントを前記第1のソース領域(116,216,316)と前記第2のソース領域(118,218)と前記サイドウォール(150,250)とに対して注入する工程(406)と、
前記N+型領域(252,352)の下部に設けられたP型領域(256,356)を形成するP型ドーパントを前記第1のソース領域(116,216)と前記第2のソース領域(118,218)と前記サイドウォール(150,250)とに対して注入する工程(408)と、
前記P型ドーパントに前記N+型領域(252,352)の下部にレトログレード・プロファイルを形成させる熱サイクルを実行する工程(408)とを有し、
前記P型ドーパントは、ワードライン(102,302)によって第1のソース領域(116,216,316)と分離されるドレイン領域(122,322)には注入されず、
前記P型ドーパントは、前記フローティングゲート型メモリアレイにおける短チャネル効果を低減し、
前記P型ドーパントを前記第1のソース領域(116,216,316)と前記第2のソース領域(118,218)と前記サイドウォール(150,250)とに対して注入する前記工程(408)が、前記P型ドーパントを前記第1のソース領域(116,216,316)の上面(215)に対して、前記第1のソース領域(116,216,316)の上面(215)に略垂直かつ前記ワードライン(102,302)に略平行な平面から測定して45度以上90度未満の角度(262)で注入する工程を含み、
前記P型ドーパントを前記第1のソース領域(116,216,316)と前記第2のソース領域(118,218)と前記サイドウォール(150,250)とに対して注入する工程(408)は、前記P型ドーパントを1平方センチメートル当たり、1×1014から1×1015の間の原子量で注入し、
前記熱サイクルを実行する工程(408)において、前記P型ドーパントに前記N+型領域(252,352)に隣接してグレーデッド濃度プロファイルを形成することを特徴とする製造方法。 - 前記P型ドーパントは、ホウ素であることを特徴とする請求項1記載の製造方法。
- 前記分離領域(112)から前記誘電体を除去する工程は、セルフアライン・ソースエッチングにより前記誘電体を除去することを特徴とする請求項1記載の製造方法。
- 前記フローティングゲート型メモリアレイは、フローティングゲート型フラッシュメモリアレイであることを特徴とする請求項1記載の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/429,150 | 2003-05-03 | ||
US10/429,150 US6773990B1 (en) | 2003-05-03 | 2003-05-03 | Method for reducing short channel effects in memory cells and related structure |
PCT/US2004/011354 WO2004100230A2 (en) | 2003-05-03 | 2004-04-13 | Method for reducing short channel effects in memory cells and related structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006525673A JP2006525673A (ja) | 2006-11-09 |
JP5258193B2 true JP5258193B2 (ja) | 2013-08-07 |
Family
ID=32825106
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006509973A Expired - Fee Related JP5258193B2 (ja) | 2003-05-03 | 2004-04-13 | フローティングゲート型メモリアレイの製造方法 |
Country Status (8)
Country | Link |
---|---|
US (2) | US6773990B1 (ja) |
JP (1) | JP5258193B2 (ja) |
KR (1) | KR20070012181A (ja) |
CN (1) | CN100433334C (ja) |
DE (1) | DE112004000753B4 (ja) |
GB (1) | GB2434030B (ja) |
TW (1) | TWI339437B (ja) |
WO (1) | WO2004100230A2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100771552B1 (ko) * | 2006-10-31 | 2007-10-31 | 주식회사 하이닉스반도체 | 숏 채널 효과가 억제되는 모스트랜지스터 및 그 제조방법 |
WO2009106433A1 (en) | 2008-02-27 | 2009-09-03 | L'air Liquide Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude | Method for forming a titanium-containing layer on a substrate using an atomic layer deposition (ald) process |
KR102070564B1 (ko) | 2013-08-09 | 2020-03-02 | 삼성전자주식회사 | 반도체 소자의 제조방법 |
US9165944B2 (en) | 2013-10-07 | 2015-10-20 | Globalfoundries Inc. | Semiconductor device including SOI butted junction to reduce short-channel penalty |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5032881A (en) * | 1990-06-29 | 1991-07-16 | National Semiconductor Corporation | Asymmetric virtual ground EPROM cell and fabrication method |
US5264384A (en) * | 1991-08-30 | 1993-11-23 | Texas Instruments Incorporated | Method of making a non-volatile memory cell |
EP0748521B1 (en) * | 1994-03-03 | 2001-11-07 | Rohm Corporation | Over-erase detection in a low voltage one transistor flash eeprom cell using fowler-nordheim programming and erase |
US5773863A (en) * | 1994-08-18 | 1998-06-30 | Sun Microsystems, Inc. | Low power, high performance junction transistor |
US5518942A (en) * | 1995-02-22 | 1996-05-21 | Alliance Semiconductor Corporation | Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant |
US6093951A (en) * | 1997-06-30 | 2000-07-25 | Sun Microsystems, Inc. | MOS devices with retrograde pocket regions |
JP3147108B2 (ja) * | 1999-01-20 | 2001-03-19 | 日本電気株式会社 | 半導体記憶装置の製造方法 |
JP2000357754A (ja) * | 1999-06-03 | 2000-12-26 | Texas Instr Inc <Ti> | Stiを有するフラッシュメモリ内にソースラインをサリサイド化する方法 |
EP1096575A1 (en) * | 1999-10-07 | 2001-05-02 | STMicroelectronics S.r.l. | Non-volatile memory cell with a single level of polysilicon and corresponding manufacturing process |
JP2002208645A (ja) * | 2001-01-09 | 2002-07-26 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置およびその製造方法 |
-
2003
- 2003-05-03 US US10/429,150 patent/US6773990B1/en not_active Expired - Lifetime
-
2004
- 2004-04-13 CN CNB2004800120169A patent/CN100433334C/zh not_active Expired - Fee Related
- 2004-04-13 GB GB0518595A patent/GB2434030B/en not_active Expired - Fee Related
- 2004-04-13 KR KR1020057020925A patent/KR20070012181A/ko not_active Application Discontinuation
- 2004-04-13 DE DE112004000753T patent/DE112004000753B4/de not_active Expired - Fee Related
- 2004-04-13 JP JP2006509973A patent/JP5258193B2/ja not_active Expired - Fee Related
- 2004-04-13 WO PCT/US2004/011354 patent/WO2004100230A2/en active Application Filing
- 2004-04-23 TW TW093111361A patent/TWI339437B/zh not_active IP Right Cessation
- 2004-05-04 US US10/839,626 patent/US6963106B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO2004100230A2 (en) | 2004-11-18 |
US6963106B1 (en) | 2005-11-08 |
DE112004000753B4 (de) | 2008-06-26 |
GB2434030A (en) | 2007-07-11 |
US6773990B1 (en) | 2004-08-10 |
GB2434030B (en) | 2008-01-09 |
CN100433334C (zh) | 2008-11-12 |
CN1826692A (zh) | 2006-08-30 |
JP2006525673A (ja) | 2006-11-09 |
DE112004000753T5 (de) | 2006-07-06 |
TW200503253A (en) | 2005-01-16 |
TWI339437B (en) | 2011-03-21 |
KR20070012181A (ko) | 2007-01-25 |
WO2004100230A3 (en) | 2005-04-21 |
GB0518595D0 (en) | 2005-10-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101878006B1 (ko) | 수직 메모리 디바이스 및 그것의 제조 방법 | |
US8962416B1 (en) | Split gate non-volatile memory cell | |
JP2006019373A (ja) | 不揮発性半導体記憶装置の製造方法および不揮発性半導体記憶装置 | |
JP2004186452A (ja) | 不揮発性半導体記憶装置およびその製造方法 | |
JP2010517270A (ja) | 不揮発性メモリデバイスを作製する方法 | |
KR20000073371A (ko) | 반도체 메모리 소자 및 그 제조방법 | |
WO2006091262A2 (en) | Nvm cell on soi and method of manufacture | |
US8664706B2 (en) | Current in one-time-programmable memory cells | |
KR100838387B1 (ko) | 부동 게이트 메모리 셀 | |
KR100585097B1 (ko) | 이이피롬 소자 및 그 제조방법 | |
JPH04209573A (ja) | 不揮発性半導体記憶装置及びその製造方法及び半導体装置 | |
JP5258193B2 (ja) | フローティングゲート型メモリアレイの製造方法 | |
KR20010030002A (ko) | 비휘발성 반도체메모리장치 및 그 제조방법 | |
KR101092010B1 (ko) | 플로팅 게이트 메모리 셀에 있어서 저 Vss 저항 및감소된 DIBL을 위한 구조 및 방법 | |
JP2006135341A (ja) | 半導体装置 | |
US6977195B1 (en) | Test structure for characterizing junction leakage current | |
KR20040010550A (ko) | 깊은 서브 0.18 미크론 플래시 메모리 셀을 위한 소스측붕소 주입에 의한 채널 도핑의 낮춤 | |
CN110739313A (zh) | 一种非易失性存储器单元、阵列及制备方法 | |
JP2004221223A (ja) | Mis型半導体装置及びその製造方法 | |
KR100733703B1 (ko) | 반도체 소자 및 이의 제조 방법 | |
KR100503366B1 (ko) | 반도체 소자 제조 방법 | |
KR100466193B1 (ko) | 반도체 메모리 소자의 제조 방법 | |
KR100458595B1 (ko) | 비휘발성 메모리 장치 및 그 제조 방법 | |
KR100247225B1 (ko) | 불휘발성 메모리 장치의 제조 방법 | |
KR100943133B1 (ko) | 반도체 소자의 트랜지스터 및 그 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20051028 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060627 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070404 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20100204 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20100616 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101021 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101109 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110201 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20111018 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111125 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20120118 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20120210 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20120720 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20120725 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20120831 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130213 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130423 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160502 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5258193 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |