JP5248918B2 - 電子部品装置及びその製造方法 - Google Patents
電子部品装置及びその製造方法 Download PDFInfo
- Publication number
- JP5248918B2 JP5248918B2 JP2008140078A JP2008140078A JP5248918B2 JP 5248918 B2 JP5248918 B2 JP 5248918B2 JP 2008140078 A JP2008140078 A JP 2008140078A JP 2008140078 A JP2008140078 A JP 2008140078A JP 5248918 B2 JP5248918 B2 JP 5248918B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- metal
- sealing
- electronic component
- post
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008140078A JP5248918B2 (ja) | 2008-05-28 | 2008-05-28 | 電子部品装置及びその製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008140078A JP5248918B2 (ja) | 2008-05-28 | 2008-05-28 | 電子部品装置及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009289926A JP2009289926A (ja) | 2009-12-10 |
| JP2009289926A5 JP2009289926A5 (enExample) | 2011-06-02 |
| JP5248918B2 true JP5248918B2 (ja) | 2013-07-31 |
Family
ID=41458869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008140078A Expired - Fee Related JP5248918B2 (ja) | 2008-05-28 | 2008-05-28 | 電子部品装置及びその製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5248918B2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10546819B2 (en) | 2016-09-15 | 2020-01-28 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6444707B2 (ja) | 2014-11-28 | 2018-12-26 | Towa株式会社 | 電子部品、その製造方法及び製造装置 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07254654A (ja) * | 1994-03-15 | 1995-10-03 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP3798620B2 (ja) * | 2000-12-04 | 2006-07-19 | 富士通株式会社 | 半導体装置の製造方法 |
| JP2003174124A (ja) * | 2001-12-04 | 2003-06-20 | Sainekkusu:Kk | 半導体装置の外部電極形成方法 |
| JP2003249607A (ja) * | 2002-02-26 | 2003-09-05 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
| JP3972183B2 (ja) * | 2002-03-07 | 2007-09-05 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
-
2008
- 2008-05-28 JP JP2008140078A patent/JP5248918B2/ja not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10546819B2 (en) | 2016-09-15 | 2020-01-28 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2009289926A (ja) | 2009-12-10 |
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