JP5248179B2 - 電子装置の製造方法 - Google Patents

電子装置の製造方法 Download PDF

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Publication number
JP5248179B2
JP5248179B2 JP2008107582A JP2008107582A JP5248179B2 JP 5248179 B2 JP5248179 B2 JP 5248179B2 JP 2008107582 A JP2008107582 A JP 2008107582A JP 2008107582 A JP2008107582 A JP 2008107582A JP 5248179 B2 JP5248179 B2 JP 5248179B2
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JP
Japan
Prior art keywords
substrate
metal
alloy
electronic device
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008107582A
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English (en)
Japanese (ja)
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JP2009260049A (ja
JP2009260049A5 (enrdf_load_stackoverflow
Inventor
啓 村山
光敏 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008107582A priority Critical patent/JP5248179B2/ja
Publication of JP2009260049A publication Critical patent/JP2009260049A/ja
Publication of JP2009260049A5 publication Critical patent/JP2009260049A5/ja
Application granted granted Critical
Publication of JP5248179B2 publication Critical patent/JP5248179B2/ja
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Landscapes

  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
JP2008107582A 2008-04-17 2008-04-17 電子装置の製造方法 Active JP5248179B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008107582A JP5248179B2 (ja) 2008-04-17 2008-04-17 電子装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008107582A JP5248179B2 (ja) 2008-04-17 2008-04-17 電子装置の製造方法

Publications (3)

Publication Number Publication Date
JP2009260049A JP2009260049A (ja) 2009-11-05
JP2009260049A5 JP2009260049A5 (enrdf_load_stackoverflow) 2011-02-24
JP5248179B2 true JP5248179B2 (ja) 2013-07-31

Family

ID=41387100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008107582A Active JP5248179B2 (ja) 2008-04-17 2008-04-17 電子装置の製造方法

Country Status (1)

Country Link
JP (1) JP5248179B2 (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130155629A1 (en) * 2011-12-19 2013-06-20 Tong Hsing Electronic Industries, Ltd. Hermetic Semiconductor Package Structure and Method for Manufacturing the same
JP6041731B2 (ja) 2013-03-27 2016-12-14 新光電気工業株式会社 インターポーザ、及び電子部品パッケージ
WO2015046209A1 (ja) * 2013-09-27 2015-04-02 京セラ株式会社 蓋体、パッケージおよび電子装置
US10453786B2 (en) 2016-01-19 2019-10-22 General Electric Company Power electronics package and method of manufacturing thereof
KR102367619B1 (ko) * 2017-02-09 2022-02-28 제네럴 일렉트릭 컴퍼니 전력 전자 패키지 및 그 제조 방법
JP2022102015A (ja) * 2020-12-25 2022-07-07 株式会社大真空 パッケージ、リッド及びパッケージの製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH105990A (ja) * 1996-06-17 1998-01-13 Matsushita Electric Ind Co Ltd 電子部品の製造方法
US5945735A (en) * 1997-01-31 1999-08-31 International Business Machines Corporation Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity
JP2001044239A (ja) * 1999-07-29 2001-02-16 Matsushita Electric Ind Co Ltd 電子部品の混載実装方法及びその混載実装工程に用いる部材
JP3905041B2 (ja) * 2003-01-07 2007-04-18 株式会社日立製作所 電子デバイスおよびその製造方法
JP4513513B2 (ja) * 2004-11-09 2010-07-28 株式会社村田製作所 電子部品の製造方法
US7745897B2 (en) * 2005-05-27 2010-06-29 Aptina Imaging Corporation Methods for packaging an image sensor and a packaged image sensor
US7569926B2 (en) * 2005-08-26 2009-08-04 Innovative Micro Technology Wafer level hermetic bond using metal alloy with raised feature

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JP2009260049A (ja) 2009-11-05

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