JP5243958B2 - マスク・レイアウトの設計する方法、該設計のためのプログラム、設計パラメータを伝達する方法、および、これらの方法を実現するプログラムならびにシステム - Google Patents

マスク・レイアウトの設計する方法、該設計のためのプログラム、設計パラメータを伝達する方法、および、これらの方法を実現するプログラムならびにシステム Download PDF

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JP5243958B2
JP5243958B2 JP2008535640A JP2008535640A JP5243958B2 JP 5243958 B2 JP5243958 B2 JP 5243958B2 JP 2008535640 A JP2008535640 A JP 2008535640A JP 2008535640 A JP2008535640 A JP 2008535640A JP 5243958 B2 JP5243958 B2 JP 5243958B2
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layer
design
band
tolerance
constraint
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JP2009511988A5 (enExample
JP2009511988A (ja
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マンスフィールド、スコット、エム
リーブマン、ラーズ、ダブリュー
グラウアー、イオアナ
クラスノペロバ、アザリア
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2008535640A 2005-10-12 2006-10-11 マスク・レイアウトの設計する方法、該設計のためのプログラム、設計パラメータを伝達する方法、および、これらの方法を実現するプログラムならびにシステム Expired - Fee Related JP5243958B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/163,264 US7266798B2 (en) 2005-10-12 2005-10-12 Designer's intent tolerance bands for proximity correction and checking
US11/163,264 2005-10-12
PCT/US2006/039701 WO2007047298A1 (en) 2005-10-12 2006-10-11 Designer's intent tolerance bands for proximity correction and checking

Publications (3)

Publication Number Publication Date
JP2009511988A JP2009511988A (ja) 2009-03-19
JP2009511988A5 JP2009511988A5 (enExample) 2009-04-30
JP5243958B2 true JP5243958B2 (ja) 2013-07-24

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JP2008535640A Expired - Fee Related JP5243958B2 (ja) 2005-10-12 2006-10-11 マスク・レイアウトの設計する方法、該設計のためのプログラム、設計パラメータを伝達する方法、および、これらの方法を実現するプログラムならびにシステム

Country Status (7)

Country Link
US (2) US7266798B2 (enExample)
EP (1) EP1952289A4 (enExample)
JP (1) JP5243958B2 (enExample)
KR (1) KR101006264B1 (enExample)
CN (1) CN101288080B (enExample)
TW (1) TW200725348A (enExample)
WO (1) WO2007047298A1 (enExample)

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US7765518B2 (en) * 2008-03-20 2010-07-27 International Business Machines Corporation System and method for implementing optical rule checking to identify and quantify corner rounding errors
US8136054B2 (en) * 2009-01-29 2012-03-13 Synopsys, Inc. Compact abbe's kernel generation using principal component analysis
US20110047519A1 (en) * 2009-05-11 2011-02-24 Juan Andres Torres Robles Layout Content Analysis for Source Mask Optimization Acceleration
US8281263B2 (en) * 2009-12-17 2012-10-02 International Business Machines Corporation Propagating design tolerances to shape tolerances for lithography
US8331646B2 (en) 2009-12-23 2012-12-11 International Business Machines Corporation Optical proximity correction for transistors using harmonic mean of gate length
US8631379B2 (en) * 2010-02-09 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Decomposing integrated circuit layout
US8392871B2 (en) 2010-04-30 2013-03-05 International Business Machines Corporation Decomposition with multiple exposures in a process window based OPC flow using tolerance bands
US8415077B2 (en) 2010-08-13 2013-04-09 International Business Machines Corporation Simultaneous optical proximity correction and decomposition for double exposure lithography
US8875063B2 (en) 2010-10-11 2014-10-28 International Business Machines Corporation Mask layout formation
US8381141B2 (en) * 2010-10-28 2013-02-19 International Business Machines Corporation Method and system for comparing lithographic processing conditions and or data preparation processes
US8298953B2 (en) 2010-12-20 2012-10-30 Infineon Technologies Ag Method for defining a separating structure within a semiconductor device
US8365108B2 (en) 2011-01-06 2013-01-29 International Business Machines Corporation Generating cut mask for double-patterning process
US9330223B2 (en) 2012-09-28 2016-05-03 International Business Machines Corporation Optical rule checking for detecting at risk structures for overlay issues
US9250535B2 (en) 2013-03-15 2016-02-02 International Business Machines Corporation Source, target and mask optimization by incorporating countour based assessments and integration over process variations
US9262578B2 (en) 2014-04-25 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit manufacturing
CN108009352A (zh) * 2017-11-30 2018-05-08 上海华力微电子有限公司 一种光刻版图的填充流程及光刻掩膜的设计方法
CN113050389B (zh) * 2021-03-30 2022-12-02 长鑫存储技术有限公司 光刻工艺条件添加方法及装置、设计系统、介质和设备

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Also Published As

Publication number Publication date
CN101288080B (zh) 2012-05-23
US7607114B2 (en) 2009-10-20
EP1952289A4 (en) 2009-07-29
EP1952289A1 (en) 2008-08-06
CN101288080A (zh) 2008-10-15
TW200725348A (en) 2007-07-01
US20070261013A1 (en) 2007-11-08
WO2007047298A1 (en) 2007-04-26
KR101006264B1 (ko) 2011-01-06
KR20080067624A (ko) 2008-07-21
US7266798B2 (en) 2007-09-04
JP2009511988A (ja) 2009-03-19
US20070083847A1 (en) 2007-04-12

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